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Commit a9c254a7 authored by Ian Abbott's avatar Ian Abbott Committed by Greg Kroah-Hartman
Browse files

staging: comedi: drivers: re-do PLX PCI 9080 BIGEND register values 



Replace `enum bigend_bits` in "plx9080.h" with a bunch of macros
defining values for the BIGEND register.  Use the prefix `PLX_BIGEND_`
for the macro names.  Make use of the `BIT(x)` and `GENMASK(h,l)` macros
to define the values.

Signed-off-by: default avatarIan Abbott <abbotti@mev.co.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent b5dcdcea

drivers/staging/comedi/drivers/cb_pcidas64.c

+1 −1
Original line number Diff line number Diff line
@@ -1294,7 +1294,7 @@ static void init_plx9080(struct comedi_device *dev) 
		readl(devpriv->plx9080_iobase + PLX_REG_CNTRL);



#ifdef __BIG_ENDIAN

	bits = BIGEND_DMA0 | BIGEND_DMA1;

	bits = PLX_BIGEND_DMA0 | PLX_BIGEND_DMA1;

#else

	bits = 0;

#endif

drivers/staging/comedi/drivers/gsc_hpdi.c

+1 −1
Original line number Diff line number Diff line
@@ -547,7 +547,7 @@ static void gsc_hpdi_init_plx9080(struct comedi_device *dev) 
	void __iomem *plx_iobase = devpriv->plx9080_mmio;



#ifdef __BIG_ENDIAN

	bits = BIGEND_DMA0 | BIGEND_DMA1;

	bits = PLX_BIGEND_DMA0 | PLX_BIGEND_DMA1;

#else

	bits = 0;

#endif

drivers/staging/comedi/drivers/plx9080.h

+18 −15
Original line number Diff line number Diff line
@@ -125,21 +125,24 @@ struct plx_dma_desc { 
/* Big/Little Endian Descriptor Register */

#define PLX_REG_BIGEND		0x000c



enum bigend_bits {

	/* use big endian ordering for configuration register accesses */

	BIGEND_CONFIG = 0x1,

	BIGEND_DIRECT_MASTER = 0x2,

	BIGEND_DIRECT_SLAVE_LOCAL0 = 0x4,

	BIGEND_ROM = 0x8,

	/*

	 * use byte lane consisting of most significant bits instead of

	 * least significant

	 */

	BIGEND_BYTE_LANE = 0x10,

	BIGEND_DIRECT_SLAVE_LOCAL1 = 0x20,

	BIGEND_DMA1 = 0x40,

	BIGEND_DMA0 = 0x80,

};

/* Configuration Register Big Endian Mode */

#define PLX_BIGEND_CONFIG	BIT(0)

/* Direct Master Big Endian Mode */

#define PLX_BIGEND_DM		BIT(1)

/* Direct Slave Address Space 0 Big Endian Mode */

#define PLX_BIGEND_DSAS0	BIT(2)

/* Direct Slave Expansion ROM Big Endian Mode */

#define PLX_BIGEND_EROM		BIT(3)

/* Big Endian Byte Lane Mode - use most significant byte lanes */

#define PLX_BIGEND_BEBLM	BIT(4)

/* Direct Slave Address Space 1 Big Endian Mode */

#define PLX_BIGEND_DSAS1	BIT(5)

/* DMA Channel 1 Big Endian Mode */

#define PLX_BIGEND_DMA1		BIT(6)

/* DMA Channel 0 Big Endian Mode */

#define PLX_BIGEND_DMA0		BIT(7)

/* DMA Channel N Big Endian Mode (N <= 1) */

#define PLX_BIGEND_DMA(n)	((n) ? PLX_BIGEND_DMA1 : PLX_BIGEND_DMA0)



/*

** Note: The Expansion ROM  stuff is only relevant to the PC environment.