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Commit a8b41ea4 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski
Browse files

Merge tag 'clk-v4.7-exynos3250' of git://linuxtv.org/snawrocki/samsung into... 

Merge tag 'clk-v4.7-exynos3250' of git://linuxtv.org/snawrocki/samsung into for-v4.7/dt-exynos3250-artik5

Addition of the Exynos3250 SoC's UART2 and MMC2 clocks.

Pull clocks used on Exynos3250-based Artik-5 board.
parents f55532a0 f6764714

drivers/clk/samsung/clk-exynos3250.c

+15 −0
Original line number Diff line number Diff line
@@ -302,10 +302,12 @@ static struct samsung_mux_clock mux_clks[] __initdata = { 


	/* SRC_FSYS */

	MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),

	MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),

	MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),

	MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),



	/* SRC_PERIL0 */

	MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),

	MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),

	MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
@@ -389,7 +391,13 @@ static struct samsung_div_clock div_clks[] __initdata = { 
		CLK_SET_RATE_PARENT, 0),

	DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),



	/* DIV_FSYS2 */

	DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,

		CLK_SET_RATE_PARENT, 0),

	DIV(CLK_DIV_MMC2, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),



	/* DIV_PERIL0 */

	DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),

	DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),

	DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
@@ -538,6 +546,8 @@ static struct samsung_gate_clock gate_clks[] __initdata = { 
		GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),

	GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",

		GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),

	GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",

		GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),

	GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",

		GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),

	GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
@@ -552,6 +562,9 @@ static struct samsung_gate_clock gate_clks[] __initdata = { 
		GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),

	GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",

		GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),



	GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",

		GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),

	GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",

		GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),

	GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
@@ -630,6 +643,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = { 
	GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),

	GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),

	GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),

	GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),

	GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),

	GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),

	GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
@@ -649,6 +663,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = { 
	GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),

	GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),

	GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),

	GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),

	GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),

	GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),

};

include/dt-bindings/clock/exynos3250.h

+10 −1
Original line number Diff line number Diff line
@@ -79,6 +79,8 @@ 
#define CLK_MOUT_CORE			58

#define CLK_MOUT_APLL			59

#define CLK_MOUT_ACLK_266_SUB		60

#define CLK_MOUT_UART2			61

#define CLK_MOUT_MMC2			62



/* Dividers */

#define CLK_DIV_GPL			64
@@ -127,6 +129,9 @@ 
#define CLK_DIV_CORE			107

#define CLK_DIV_HPM			108

#define CLK_DIV_COPY			109

#define CLK_DIV_UART2			110

#define CLK_DIV_MMC2_PRE		111

#define CLK_DIV_MMC2			112



/* Gates */

#define CLK_ASYNC_G3D			128
@@ -223,6 +228,8 @@ 
#define CLK_BLOCK_MFC			219

#define CLK_BLOCK_CAM			220

#define CLK_SMIES			221

#define CLK_UART2			222

#define CLK_SDMMC2			223



/* Special clocks */

#define CLK_SCLK_JPEG			224
@@ -249,12 +256,14 @@ 
#define CLK_SCLK_SPI0			245

#define CLK_SCLK_UART1			246

#define CLK_SCLK_UART0			247

#define CLK_SCLK_UART2			248

#define CLK_SCLK_MMC2			249



/*

 * Total number of clocks of main CMU.

 * NOTE: Must be equal to last clock ID increased by one.

 */

#define CLK_NR_CLKS			248

#define CLK_NR_CLKS			250



/*

 * CMU DMC