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Commit a727eaf6 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'drivers-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next 

Pull ARM SoC driver changes from Olof Johansson:
 "SoC-near driver changes that we're merging through our tree.  Mostly
  because they depend on other changes we have staged, but in some cases
  because the driver maintainers preferred that we did it this way.

  This contains a largeish cleanup series of the omap_l3_noc bus driver,
  cpuidle rework for Exynos, some reset driver conversions and a long
  branch of TI EDMA fixes and cleanups, with more to come next release.

  The TI EDMA cleanups is a shared branch with the dmaengine tree, with
  a handful of Davinci-specific fixes on top.

  After discussion at last year's KS (and some more on the mailing
  lists), we are here adding a drivers/soc directory.  The purpose of
  this is to keep per-vendor shared code that's needed by different
  drivers but that doesn't fit into the MFD (nor drivers/platform)
  model.  We expect to keep merging contents for this hierarchy through
  arm-soc so we can keep an eye on what the vendors keep adding here and
  not making it a free-for-all to shove in crazy stuff"

* tag 'drivers-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (101 commits)
  cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM
  tty: serial: msm: Remove direct access to GSBI
  power: reset: keystone-reset: introduce keystone reset driver
  Documentation: dt: add bindings for keystone pll control controller
  Documentation: dt: add bindings for keystone reset driver
  soc: qcom: fix of_device_id table
  ARM: EXYNOS: Fix kernel panic when unplugging CPU1 on exynos
  ARM: EXYNOS: Move the driver to drivers/cpuidle directory
  ARM: EXYNOS: Cleanup all unneeded headers from cpuidle.c
  ARM: EXYNOS: Pass the AFTR callback to the platform_data
  ARM: EXYNOS: Move S5P_CHECK_SLEEP into pm.c
  ARM: EXYNOS: Move the power sequence call in the cpu_pm notifier
  ARM: EXYNOS: Move the AFTR state function into pm.c
  ARM: EXYNOS: Encapsulate the AFTR code into a function
  ARM: EXYNOS: Disable cpuidle for exynos5440
  ARM: EXYNOS: Encapsulate boot vector code into a function for cpuidle
  ARM: EXYNOS: Pass wakeup mask parameter to function for cpuidle
  ARM: EXYNOS: Remove ifdef for scu_enable in pm
  ARM: EXYNOS: Move scu_enable in the cpu_pm notifier
  ARM: EXYNOS: Use the cpu_pm notifier for pm
  ...
parents 755a9ba7 45e70b7d

Documentation/ABI/testing/sysfs-platform-brcmstb-gisb-arb

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What:		/sys/devices/../../gisb_arb_timeout

Date:		May 2014

KernelVersion:	3.17

Contact:	Florian Fainelli <f.fainelli@gmail.com>

Description:

		Returns the currently configured raw timeout value of the

		Broadcom Set Top Box internal GISB bus arbiter. Minimum value

		is 1, and maximum value is 0xffffffff.

Documentation/devicetree/bindings/arm/omap/l3-noc.txt

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@@ -6,6 +6,8 @@ provided by Arteris. 
Required properties:

- compatible : Should be "ti,omap3-l3-smx" for OMAP3 family

               Should be "ti,omap4-l3-noc" for OMAP4 family

	       Should be "ti,dra7-l3-noc" for DRA7 family

               Should be "ti,am4372-l3-noc" for AM43 family

- reg:	Contains L3 register address range for each noc domain.

- ti,hwmods: "l3_main_1", ... One hwmod for each noc domain.

Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt

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Broadcom GISB bus Arbiter controller



Required properties:



- compatible: should be "brcm,gisb-arb"

- reg: specifies the base physical address and size of the registers

- interrupt-parent: specifies the phandle to the parent interrupt controller

  this arbiter gets interrupt line from

- interrupts: specifies the two interrupts (timeout and TEA) to be used from

  the parent interrupt controller



Optional properties:



- brcm,gisb-arb-master-mask: 32-bits wide bitmask used to specify which GISB

  masters are valid at the system level

- brcm,gisb-arb-master-names: string list of the litteral name of the GISB

  masters. Should match the number of bits set in brcm,gisb-master-mask and

  the order in which they appear



Example:



gisb-arb@f0400000 {

	compatible = "brcm,gisb-arb";

	reg = <0xf0400000 0x800>;

	interrupts = <0>, <2>;

	interrupt-parent = <&sun_l2_intc>;



	brcm,gisb-arb-master-mask = <0x7>;

	brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0";

};

Documentation/devicetree/bindings/clock/ti-keystone-pllctrl.txt

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* Device tree bindings for Texas Instruments keystone pll controller



The main pll controller used to drive theC66x CorePacs, the switch fabric,

and a majority of the peripheral clocks (all but the ARM CorePacs, DDR3 and

the NETCP modules) requires a PLL Controller to manage the various clock

divisions, gating, and synchronization.



Required properties:



- compatible:		"ti,keystone-pllctrl", "syscon"



- reg:			contains offset/length value for pll controller

			registers space.



Example:



pllctrl: pll-controller@0x02310000 {

	compatible = "ti,keystone-pllctrl", "syscon";

	reg = <0x02310000 0x200>;

};

Documentation/devicetree/bindings/dma/ti-edma.txt

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@@ -2,11 +2,8 @@ TI EDMA 


Required properties:

- compatible : "ti,edma3"

- ti,edma-regions: Number of regions

- ti,edma-slots: Number of slots

- #dma-cells: Should be set to <1>

              Clients should use a single channel number per DMA request.

- dma-channels: Specify total DMA channels per CC

- reg: Memory map for accessing module

- interrupt-parent: Interrupt controller the interrupt is routed through

- interrupts: Exactly 3 interrupts need to be specified in the order:
@@ -17,6 +14,13 @@ Optional properties: 
- ti,hwmods: Name of the hwmods associated to the EDMA

- ti,edma-xbar-event-map: Crossbar event to channel map



Deprecated properties:

Listed here in case one wants to boot an old kernel with new DTB. These

properties might need to be added to the new DTS files.

- ti,edma-regions: Number of regions

- ti,edma-slots: Number of slots

- dma-channels: Specify total DMA channels per CC



Example:



edma: edma@49000000 {
@@ -26,9 +30,6 @@ edma: edma@49000000 { 
	compatible = "ti,edma3";

	ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";

	#dma-cells = <1>;

	dma-channels = <64>;

	ti,edma-regions = <4>;

	ti,edma-slots = <256>;

	ti,edma-xbar-event-map = /bits/ 16 <1 12

					    2 13>;

};