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Commit a6ece7ff authored by yanyang1's avatar yanyang1 Committed by Alex Deucher
Browse files

drm/amd/powerplay: Add smc_sk firmware to baffin & ellesmere. 



update relational h files.

Signed-off-by: default avataryanyang1 <Young.Yang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 735f002b

drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h

+1 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ 
#define UCODE_ID_IH_REG_RESTORE   11

#define UCODE_ID_VBIOS            12

#define UCODE_ID_MISC_METADATA    13

#define UCODE_ID_SMU_SK		      14

#define UCODE_ID_RLC_SCRATCH      32

#define UCODE_ID_RLC_SRM_ARAM     33

#define UCODE_ID_RLC_SRM_DRAM     34

drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h

+8 −2
Original line number Diff line number Diff line
@@ -71,8 +71,12 @@ struct SMU_SclkSetting { 
	uint16_t    Pcc_fcw_int;

	uint8_t     PllRange;

	uint8_t     SSc_En;

	uint16_t    Sclk_slew_rate;

	uint16_t    Pcc_up_slew_rate;

	uint16_t    Pcc_down_slew_rate;

	uint16_t    Fcw1_int;

	uint16_t    Fcw1_frac;

	uint16_t    Sclk_ss_slew_rate;

};

typedef struct SMU_SclkSetting SMU_SclkSetting;
@@ -120,7 +124,8 @@ struct SMU74_Discrete_Ulv { 
	uint16_t    VddcOffset;

	uint8_t     VddcOffsetVid;

	uint8_t     VddcPhase;

	uint32_t    Reserved;

	uint16_t    BifSclkDfs;

	uint16_t    Reserved;

};



typedef struct SMU74_Discrete_Ulv SMU74_Discrete_Ulv;
@@ -155,7 +160,8 @@ struct SMU74_Discrete_LinkLevel { 
	uint8_t     SPC;

	uint32_t    DownThreshold;

	uint32_t    UpThreshold;

	uint32_t    Reserved;

	uint16_t    BifSclkDfs;

	uint16_t    Reserved;

};



typedef struct SMU74_Discrete_LinkLevel SMU74_Discrete_LinkLevel;

drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h

+1 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ 
#define UCODE_ID_IH_REG_RESTORE   11

#define UCODE_ID_VBIOS            12

#define UCODE_ID_MISC_METADATA    13

#define UCODE_ID_SMU_SK		      14

#define UCODE_ID_RLC_SCRATCH      32

#define UCODE_ID_RLC_SRM_ARAM     33

#define UCODE_ID_RLC_SRM_DRAM     34