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Commit a6cb74cb authored by Jonghwa Lee's avatar Jonghwa Lee Committed by Sylwester Nawrocki
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clk: samsung: exynos5433: Fix wrong registers of PCLK_GSCL_SMMU clocks 



This fixes register assignment in the CLK_PCLK_SMMU_GSCL{1,2}
clocks definition.

Signed-off-by: default avatarJonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
parent 3795e0f6

drivers/clk/samsung/clk-exynos5433.c

+2 −2
Original line number Diff line number Diff line
@@ -3411,11 +3411,11 @@ static struct samsung_gate_clock gscl_gate_clks[] __initdata = { 


	/* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */

	GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user",

		ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),

		ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),



	/* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */

	GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user",

		ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),

		ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),

};



static struct samsung_cmu_info gscl_cmu_info __initdata = {