Merge remote-tracking branches 'asoc/topic/fsl', 'asoc/topic/fsl-card',...

Audio complex for Eukrea boards with tlv320aic23 codec.

Required properties:

  - compatible		: "eukrea,asoc-tlv320"

  - eukrea,model	: The user-visible name of this sound complex.

  - ssi-controller	: The phandle of the SSI controller.

  - fsl,mux-int-port	: The internal port of the i.MX audio muxer (AUDMUX).

  - fsl,mux-ext-port	: The external port of the i.MX audio muxer.

Note: The AUDMUX port numbering should start at 1, which is consistent with

  - clock-names		: Includes the following entries:

	"core"		  The core clock used to access registers

	"extal"		The esai baud clock for esai controller used to derive

			HCK, SCK and FS.

	"fsys"		The system clock derived from ahb clock used to derive

			HCK, SCK and FS.

	"extal"		  The esai baud clock for esai controller used to

			  derive HCK, SCK and FS.

	"fsys"		  The system clock derived from ahb clock used to

			  derive HCK, SCK and FS.

  - fsl,fifo-depth: The number of elements in the transmit and receive FIFOs.

    This number is the maximum allowed value for TFCR[TFWM] or RFCR[RFWM].

  - fsl,fifo-depth	: The number of elements in the transmit and receive

			  FIFOs. This number is the maximum allowed value for

			  TFCR[TFWM] or RFCR[RFWM].

  - fsl,esai-synchronous: This is a boolean property. If present, indicating

    that ESAI would work in the synchronous mode, which means all the settings

    for Receiving would be duplicated from Transmition related registers.

			  that ESAI would work in the synchronous mode, which

			  means all the settings for Receiving would be

			  duplicated from Transmition related registers.

  - big-endian : If this property is absent, the native endian mode will

    be in use as default, or the big endian mode will be in use for all the

    device registers.

  - big-endian		: If this property is absent, the native endian mode

			  will be in use as default, or the big endian mode

			  will be in use for all the device registers.

Example:

  - clocks		: Contains an entry for each entry in clock-names.

  - clock-names		: Includes the following entries:

	"core"		The core clock of spdif controller

	"core"		  The core clock of spdif controller.

	"rxtx<0-7>"	  Clock source list for tx and rx clock.

			This clock list should be identical to

			the source list connecting to the spdif

			clock mux in "SPDIF Transceiver Clock

			Diagram" of SoC reference manual. It

			can also be referred to TxClk_Source

			bit of register SPDIF_STC.

   - big-endian : If this property is absent, the native endian mode will

   be in use as default, or the big endian mode will be in use for all the

   device registers.

			  This clock list should be identical to the source

			  list connecting to the spdif clock mux in "SPDIF

			  Transceiver Clock Diagram" of SoC reference manual.

			  It can also be referred to TxClk_Source bit of

			  register SPDIF_STC.

   - big-endian		: If this property is absent, the native endian mode

			  will be in use as default, or the big endian mode

			  will be in use for all the device registers.

Example:

serial interfaces with frame synchronization such as I2S, AC97, TDM, and

codec/DSP interfaces.

Required properties:

- compatible: Compatible list, contains "fsl,vf610-sai" or "fsl,imx6sx-sai".

  - compatible		: Compatible list, contains "fsl,vf610-sai" or

			  "fsl,imx6sx-sai".

  - reg			: Offset and length of the register set for the device.

  - clocks		: Must contain an entry for each entry in clock-names.

- clock-names : Must include the "bus" for register access and "mclk1" "mclk2"

  "mclk3" for bit clock and frame clock providing.

  - clock-names		: Must include the "bus" for register access and

			  "mclk1", "mclk2", "mclk3" for bit clock and frame

			  clock providing.

  - dmas		: Generic dma devicetree binding as described in

			  Documentation/devicetree/bindings/dma/dma.txt.

  - dma-names		: Two dmas have to be defined, "tx" and "rx".

  - pinctrl-names	: Must contain a "default" entry.

- pinctrl-NNN: One property must exist for each entry in pinctrl-names.

  See ../pinctrl/pinctrl-bindings.txt for details of the property values.

- big-endian: Boolean property, required if all the FTM_PWM registers

  are big-endian rather than little-endian.

- lsb-first: Configures whether the LSB or the MSB is transmitted first for

  the fifo data. If this property is absent, the MSB is transmitted first as

  default, or the LSB is transmitted first.

  - pinctrl-NNN		: One property must exist for each entry in

			  pinctrl-names. See ../pinctrl/pinctrl-bindings.txt

			  for details of the property values.

  - big-endian		: Boolean property, required if all the FTM_PWM

			  registers are big-endian rather than little-endian.

  - lsb-first		: Configures whether the LSB or the MSB is transmitted

			  first for the fifo data. If this property is absent,

			  the MSB is transmitted first as default, or the LSB

			  is transmitted first.

  - fsl,sai-synchronous-rx: This is a boolean property. If present, indicating

  that SAI will work in the synchronous mode (sync Tx with Rx) which means

  both the transimitter and receiver will send and receive data by following

			  that SAI will work in the synchronous mode (sync Tx

			  with Rx) which means both the transimitter and the

			  receiver will send and receive data by following

			  receiver's bit clocks and frame sync clocks.

  - fsl,sai-asynchronous: This is a boolean property. If present, indicating

  that SAI will work in the asynchronous mode, which means both transimitter

  and receiver will send and receive data by following their own bit clocks

  and frame sync clocks separately.

			  that SAI will work in the asynchronous mode, which

			  means both transimitter and receiver will send and

			  receive data by following their own bit clocks and

			  frame sync clocks separately.

Note:

- If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the

Freescale i.MX audio complex with SGTL5000 codec

Required properties:

  - compatible		: "fsl,imx-audio-sgtl5000"

  - model		: The user-visible name of this sound complex

  - ssi-controller	: The phandle of the i.MX SSI controller

  - audio-codec		: The phandle of the SGTL5000 audio codec

  - audio-routing	: A list of the connections between audio components.

  Each entry is a pair of strings, the first being the connection's sink,

  the second being the connection's source. Valid names could be power

  supplies, SGTL5000 pins, and the jacks on the board:

			  Each entry is a pair of strings, the first being the

			  connection's sink, the second being the connection's

			  source. Valid names could be power supplies, SGTL5000

			  pins, and the jacks on the board:

			  Power supplies:

			   * Mic Bias

			   * Ext Spk

  - mux-int-port	: The internal port of the i.MX audio muxer (AUDMUX)

  - mux-ext-port	: The external port of the i.MX audio muxer

Note: The AUDMUX port numbering should start at 1, which is consistent with