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Commit a65851af authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: Make data/link N value power of two 

The BIOS uses power of two values for the data/link N value.

Follow suit to make the Zotac DP to dual-HDMI dongle work.

v2: Clean up the magic numbers and defines
    Change the N clamping to be a bit easier on the eye
    Rename intel_reduce_ratio to intel_reduce_m_n_ratio

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49402


Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=59810


Tested-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent ae4edb80

drivers/gpu/drm/i915/i915_reg.h

+4 −8
Original line number Diff line number Diff line
@@ -2652,14 +2652,14 @@ 
#define _PIPEB_GMCH_DATA_M			0x71050



/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */

#define   PIPE_GMCH_DATA_M_TU_SIZE_MASK		(0x3f << 25)

#define   PIPE_GMCH_DATA_M_TU_SIZE_SHIFT	25

#define  TU_SIZE(x)             (((x)-1) << 25) /* default size 64 */

#define  TU_SIZE_MASK           (0x3f << 25)



#define   PIPE_GMCH_DATA_M_MASK			(0xffffff)

#define  DATA_LINK_M_N_MASK	(0xffffff)

#define  DATA_LINK_N_MAX	(0x800000)



#define _PIPEA_GMCH_DATA_N			0x70054

#define _PIPEB_GMCH_DATA_N			0x71054

#define   PIPE_GMCH_DATA_N_MASK			(0xffffff)



/*

 * Computing Link M and N values for the Display Port link
@@ -2674,11 +2674,9 @@ 


#define _PIPEA_DP_LINK_M				0x70060

#define _PIPEB_DP_LINK_M				0x71060

#define   PIPEA_DP_LINK_M_MASK			(0xffffff)



#define _PIPEA_DP_LINK_N				0x70064

#define _PIPEB_DP_LINK_N				0x71064

#define   PIPEA_DP_LINK_N_MASK			(0xffffff)



#define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)

#define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
@@ -3404,8 +3402,6 @@ 




#define _PIPEA_DATA_M1           (dev_priv->info->display_mmio_offset + 0x60030)

#define  TU_SIZE(x)             (((x)-1) << 25) /* default size 64 */

#define  TU_SIZE_MASK           0x7e000000

#define  PIPE_DATA_M1_OFFSET    0

#define _PIPEA_DATA_N1           (dev_priv->info->display_mmio_offset + 0x60034)

#define  PIPE_DATA_N1_OFFSET    0

drivers/gpu/drm/i915/intel_display.c

+18 −8
Original line number Diff line number Diff line
@@ -4084,26 +4084,36 @@ static int i830_get_display_clock_speed(struct drm_device *dev) 
}



static void

intel_reduce_ratio(uint32_t *num, uint32_t *den)

intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)

{

	while (*num > 0xffffff || *den > 0xffffff) {

	while (*num > DATA_LINK_M_N_MASK ||

	       *den > DATA_LINK_M_N_MASK) {

		*num >>= 1;

		*den >>= 1;

	}

}



static void compute_m_n(unsigned int m, unsigned int n,

			uint32_t *ret_m, uint32_t *ret_n)

{

	*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);

	*ret_m = div_u64((uint64_t) m * *ret_n, n);

	intel_reduce_m_n_ratio(ret_m, ret_n);

}



void

intel_link_compute_m_n(int bits_per_pixel, int nlanes,

		       int pixel_clock, int link_clock,

		       struct intel_link_m_n *m_n)

{

	m_n->tu = 64;

	m_n->gmch_m = bits_per_pixel * pixel_clock;

	m_n->gmch_n = link_clock * nlanes * 8;

	intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);

	m_n->link_m = pixel_clock;

	m_n->link_n = link_clock;

	intel_reduce_ratio(&m_n->link_m, &m_n->link_n);



	compute_m_n(bits_per_pixel * pixel_clock,

		    link_clock * nlanes * 8,

		    &m_n->gmch_m, &m_n->gmch_n);



	compute_m_n(pixel_clock, link_clock,

		    &m_n->link_m, &m_n->link_n);

}



static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)