Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a64424d7 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-4.7' of git://people.freedesktop.org/~agd5f/linux into drm-next 

This is the first big radeon/amdgpu pull request for 4.7.  Highlights:
    - Polaris support in amdgpu
      Current display stack on par with other asics, for advanced features DAL is required
      Power management support
      Support for GFX, Compute, SDMA, UVD, VCE
    - VCE and UVD init/fini cleanup in radeon
    - GPUVM improvements
    - Scheduler improvements
    - Clockgating improvements
    - Powerplay improvements
    - TTM changes to support driver specific LRU update mechanism
    - Radeon support for new Mesa features
    - ASYNC pageflip support for radeon
    - Lots of bug fixes and code cleanups

* 'drm-next-4.7' of git://people.freedesktop.org/~agd5f/linux: (180 commits)
  drm/amdgpu: Replace rcu_assign_pointer() with RCU_INIT_POINTER()
  drm/amdgpu: use drm_mode_vrefresh() rather than mode->vrefresh
  drm/amdgpu/uvd6: add bypass support for fiji (v3)
  drm/amdgpu/fiji: set UVD CG state when enabling UVD DPM (v2)
  drm/powerplay: add missing clockgating callback for tonga
  drm/amdgpu: Constify some tables
  drm/amd/powerplay: Delete dead struct declaration
  drm/amd/powerplay/hwmgr: don't add invalid voltage
  drm/amd/powerplay/hwmgr: prevent VDDC from exceeding 2V
  MAINTAINERS: Remove unneded wildcard for the Radeon/AMDGPU drivers
  drm/radeon: add cayman VM support for append packet.
  drm/amd/amdgpu: Add debugfs entries for smc/didt/pcie
  drm/amd/amdgpu: Drop print_status callbacks.
  drm/amd/powerplay: revise reading/writing pptable on Polaris10
  drm/amd/powerplay: revise reading/writing pptable on Tonga
  drm/amd/powerplay: revise reading/writing pptable on Fiji
  drm/amd/powerplay: revise caching the soft pptable and add it's size
  drm/amd/powerplay: add dpm force multiple levels on cz/tonga/fiji/polaris (v2)
  drm/amd/powerplay: fix fan speed percent setting error on Polaris10
  drm/amd/powerplay: fix bug dpm can't work when resume back on Polaris
  ...
parents 0552f765 84fae133

MAINTAINERS

+2 −2
Original line number Diff line number Diff line
@@ -3790,9 +3790,9 @@ L: dri-devel@lists.freedesktop.org 
T:	git git://people.freedesktop.org/~agd5f/linux

S:	Supported

F:	drivers/gpu/drm/radeon/

F:	include/uapi/drm/radeon*

F:	include/uapi/drm/radeon_drm.h

F:	drivers/gpu/drm/amd/

F:	include/uapi/drm/amdgpu*

F:	include/uapi/drm/amdgpu_drm.h



DRM PANEL DRIVERS

M:	Thierry Reding <thierry.reding@gmail.com>

drivers/gpu/drm/amd/acp/acp_hw.c

+1 −1
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ 


#define mmACP_AZALIA_I2S_SELECT 0x51d4



int amd_acp_hw_init(void *cgs_device,

int amd_acp_hw_init(struct cgs_device *cgs_device,

		    unsigned acp_version_major, unsigned acp_version_minor)

{

	unsigned int acp_mode = ACP_MODE_I2S;

drivers/gpu/drm/amd/acp/include/acp_gfx_if.h

+1 −1
Original line number Diff line number Diff line
@@ -28,7 +28,7 @@ 
#include "cgs_linux.h"

#include "cgs_common.h"



int amd_acp_hw_init(void *cgs_device,

int amd_acp_hw_init(struct cgs_device *cgs_device,

		    unsigned acp_version_major, unsigned acp_version_minor);



#endif /* _ACP_GFX_IF_H */

drivers/gpu/drm/amd/amdgpu/Kconfig

+10 −0
Original line number Diff line number Diff line
@@ -15,3 +15,13 @@ config DRM_AMDGPU_USERPTR 
	help

	  This option selects CONFIG_MMU_NOTIFIER if it isn't already

	  selected to enabled full userptr support.



config DRM_AMDGPU_GART_DEBUGFS

	bool "Allow GART access through debugfs"

	depends on DRM_AMDGPU

	depends on DEBUG_FS

	default n

	help

	  Selecting this option creates a debugfs file to inspect the mapped

	  pages. Uses more memory for housekeeping, enable only for debugging.

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+79 −38
Original line number Diff line number Diff line
@@ -302,6 +302,8 @@ struct amdgpu_ring_funcs { 
	void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);

	/* pad the indirect buffer to the necessary number of dw */

	void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);

	unsigned (*init_cond_exec)(struct amdgpu_ring *ring);

	void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);

};



/*
@@ -391,6 +393,14 @@ unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 
/*

 * TTM.

 */



#define AMDGPU_TTM_LRU_SIZE	20



struct amdgpu_mman_lru {

	struct list_head		*lru[TTM_NUM_MEM_TYPES];

	struct list_head		*swap_lru;

};



struct amdgpu_mman {

	struct ttm_bo_global_ref        bo_global_ref;

	struct drm_global_reference	mem_global_ref;
@@ -408,6 +418,9 @@ struct amdgpu_mman { 
	struct amdgpu_ring			*buffer_funcs_ring;

	/* Scheduler entity for buffer moves */

	struct amd_sched_entity			entity;



	/* custom LRU management */

	struct amdgpu_mman_lru			log2_size[AMDGPU_TTM_LRU_SIZE];

};



int amdgpu_copy_buffer(struct amdgpu_ring *ring,
@@ -586,6 +599,9 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, 
		     struct amdgpu_sync *sync,

		     struct reservation_object *resv,

		     void *owner);

bool amdgpu_sync_is_idle(struct amdgpu_sync *sync);

int amdgpu_sync_cycle_fences(struct amdgpu_sync *dst, struct amdgpu_sync *src,

			     struct fence *fence);

struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);

int amdgpu_sync_wait(struct amdgpu_sync *sync);

void amdgpu_sync_free(struct amdgpu_sync *sync);
@@ -609,8 +625,9 @@ struct amdgpu_gart { 
	unsigned			num_gpu_pages;

	unsigned			num_cpu_pages;

	unsigned			table_size;

#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS

	struct page			**pages;

	dma_addr_t			*pages_addr;

#endif

	bool				ready;

	const struct amdgpu_gart_funcs *gart_funcs;

};
@@ -742,16 +759,19 @@ enum amdgpu_ring_type { 
	AMDGPU_RING_TYPE_VCE

};



extern struct amd_sched_backend_ops amdgpu_sched_ops;

extern const struct amd_sched_backend_ops amdgpu_sched_ops;



int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,

		     struct amdgpu_job **job);

int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,

			     struct amdgpu_job **job);



void amdgpu_job_free(struct amdgpu_job *job);

void amdgpu_job_free_func(struct kref *refcount);

int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,

		      struct amd_sched_entity *entity, void *owner,

		      struct fence **f);

void amdgpu_job_timeout_func(struct work_struct *work);



struct amdgpu_ring {

	struct amdgpu_device		*adev;
@@ -788,6 +808,9 @@ struct amdgpu_ring { 
	struct amdgpu_ctx	*current_ctx;

	enum amdgpu_ring_type	type;

	char			name[16];

	unsigned		cond_exe_offs;

	u64				cond_exe_gpu_addr;

	volatile u32	*cond_exe_cpu_addr;

};



/*
@@ -830,13 +853,6 @@ struct amdgpu_vm_pt { 
	uint64_t			addr;

};



struct amdgpu_vm_id {

	struct amdgpu_vm_manager_id	*mgr_id;

	uint64_t			pd_gpu_addr;

	/* last flushed PD/PT update */

	struct fence			*flushed_updates;

};



struct amdgpu_vm {

	/* tree of virtual addresses mapped */

	struct rb_root		va;
@@ -862,7 +878,7 @@ struct amdgpu_vm { 
	struct amdgpu_vm_pt	*page_tables;



	/* for id and flush management per ring */

	struct amdgpu_vm_id	ids[AMDGPU_MAX_RINGS];

	struct amdgpu_vm_id	*ids[AMDGPU_MAX_RINGS];



	/* protecting freed */

	spinlock_t		freed_lock;
@@ -871,11 +887,18 @@ struct amdgpu_vm { 
	struct amd_sched_entity	entity;

};



struct amdgpu_vm_manager_id {

struct amdgpu_vm_id {

	struct list_head	list;

	struct fence		*active;

	struct fence		*first;

	struct amdgpu_sync	active;

	struct fence		*last_flush;

	struct amdgpu_ring      *last_user;

	atomic_long_t		owner;



	uint64_t		pd_gpu_addr;

	/* last flushed PD/PT update */

	struct fence		*flushed_updates;



	uint32_t		gds_base;

	uint32_t		gds_size;

	uint32_t		gws_base;
@@ -889,7 +912,7 @@ struct amdgpu_vm_manager { 
	struct mutex				lock;

	unsigned				num_ids;

	struct list_head			ids_lru;

	struct amdgpu_vm_manager_id		ids[AMDGPU_NUM_VM];

	struct amdgpu_vm_id			ids[AMDGPU_NUM_VM];



	uint32_t				max_pfn;

	/* vram base address for page table entry  */
@@ -916,7 +939,7 @@ void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, 
int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,

		      struct amdgpu_sync *sync, struct fence *fence,

		      unsigned *vm_id, uint64_t *vm_pd_addr);

void amdgpu_vm_flush(struct amdgpu_ring *ring,

int amdgpu_vm_flush(struct amdgpu_ring *ring,

		    unsigned vm_id, uint64_t pd_addr,

		    uint32_t gds_base, uint32_t gds_size,

		    uint32_t gws_base, uint32_t gws_size,
@@ -1026,6 +1049,11 @@ void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 
 */

#include "clearstate_defs.h"



struct amdgpu_rlc_funcs {

	void (*enter_safe_mode)(struct amdgpu_device *adev);

	void (*exit_safe_mode)(struct amdgpu_device *adev);

};



struct amdgpu_rlc {

	/* for power gating */

	struct amdgpu_bo	*save_restore_obj;
@@ -1044,6 +1072,24 @@ struct amdgpu_rlc { 
	uint64_t		cp_table_gpu_addr;

	volatile uint32_t	*cp_table_ptr;

	u32                     cp_table_size;



	/* safe mode for updating CG/PG state */

	bool in_safe_mode;

	const struct amdgpu_rlc_funcs *funcs;



	/* for firmware data */

	u32 save_and_restore_offset;

	u32 clear_state_descriptor_offset;

	u32 avail_scratch_ram_locations;

	u32 reg_restore_list_size;

	u32 reg_list_format_start;

	u32 reg_list_format_separate_start;

	u32 starting_offsets_start;

	u32 reg_list_format_size_bytes;

	u32 reg_list_size_bytes;



	u32 *register_list_format;

	u32 *register_restore;

};



struct amdgpu_mec {
@@ -1582,9 +1628,11 @@ void amdgpu_get_pcie_info(struct amdgpu_device *adev); 
/*

 * UVD

 */

#define AMDGPU_MAX_UVD_HANDLES	10

#define AMDGPU_UVD_STACK_SIZE	(1024*1024)

#define AMDGPU_UVD_HEAP_SIZE	(1024*1024)

#define AMDGPU_DEFAULT_UVD_HANDLES	10

#define AMDGPU_MAX_UVD_HANDLES		40

#define AMDGPU_UVD_STACK_SIZE		(200*1024)

#define AMDGPU_UVD_HEAP_SIZE		(256*1024)

#define AMDGPU_UVD_SESSION_SIZE		(50*1024)

#define AMDGPU_UVD_FIRMWARE_OFFSET	256



struct amdgpu_uvd {
@@ -1592,6 +1640,7 @@ struct amdgpu_uvd { 
	void			*cpu_addr;

	uint64_t		gpu_addr;

	void			*saved_bo;

	unsigned		max_handles;

	atomic_t		handles[AMDGPU_MAX_UVD_HANDLES];

	struct drm_file		*filp[AMDGPU_MAX_UVD_HANDLES];

	struct delayed_work	idle_work;
@@ -1690,12 +1739,12 @@ static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} 
 * Debugfs

 */

struct amdgpu_debugfs {

	struct drm_info_list	*files;

	const struct drm_info_list	*files;

	unsigned		num_files;

};



int amdgpu_debugfs_add_files(struct amdgpu_device *adev,

			     struct drm_info_list *files,

			     const struct drm_info_list *files,

			     unsigned nfiles);

int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
@@ -1854,15 +1903,8 @@ struct amdgpu_atcs { 
/*

 * CGS

 */

void *amdgpu_cgs_create_device(struct amdgpu_device *adev);

void amdgpu_cgs_destroy_device(void *cgs_device);





/*

 * CGS

 */

void *amdgpu_cgs_create_device(struct amdgpu_device *adev);

void amdgpu_cgs_destroy_device(void *cgs_device);

struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);

void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);





/* GPU virtualization */
@@ -1903,7 +1945,6 @@ struct amdgpu_device { 
	int				usec_timeout;

	const struct amdgpu_asic_funcs	*asic_funcs;

	bool				shutdown;

	bool				suspend;

	bool				need_dma32;

	bool				accel_working;

	struct work_struct 		reset_work;
@@ -1912,7 +1953,7 @@ struct amdgpu_device { 
	struct amdgpu_debugfs		debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];

	unsigned 			debugfs_count;

#if defined(CONFIG_DEBUG_FS)

	struct dentry			*debugfs_regs;

	struct dentry			*debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];

#endif

	struct amdgpu_atif		atif;

	struct amdgpu_atcs		atcs;
@@ -1925,7 +1966,6 @@ struct amdgpu_device { 
	/* BIOS */

	uint8_t				*bios;

	bool				is_atom_bios;

	uint16_t			bios_header_start;

	struct amdgpu_bo		*stollen_vga_memory;

	uint32_t			bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
@@ -2181,6 +2221,8 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 
#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))

#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))

#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))

#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))

#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))

#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))

#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))

#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
@@ -2337,7 +2379,7 @@ static inline void amdgpu_unregister_atpx_handler(void) {} 
 * KMS

 */

extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];

extern int amdgpu_max_kms_ioctl;

extern const int amdgpu_max_kms_ioctl;



int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);

int amdgpu_driver_unload_kms(struct drm_device *dev);
@@ -2396,5 +2438,4 @@ amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 
		       uint64_t addr, struct amdgpu_bo **bo);



#include "amdgpu_object.h"



#endif