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Commit a52bb15b authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: Rewrite BXT HPD code to conform to pre-existing style 



Rewrite the BXT hpd setup to match the way we do it on other platforms:
- Throw out BXT_HOTPLUG_CTL since it's the same as PCH_PORT_HOTPLUG
- Enable the HPD bits in the DE port IER in gen8_de_irq_postinstall()
- Update DE port IMR using bdw_update_port_irq()

Also throw out port D from bxt_port_hotplug_long_detect() since BXT only
goes up to C.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 40e56410

drivers/gpu/drm/i915/i915_irq.c

+13 −23
Original line number Original line Diff line number Diff line
@@ -1300,8 +1300,6 @@ static bool bxt_port_hotplug_long_detect(enum port port, u32 val) 
		return val & PORTB_HOTPLUG_LONG_DETECT;

		return val & PORTB_HOTPLUG_LONG_DETECT;

	case PORT_C:

	case PORT_C:

		return val & PORTC_HOTPLUG_LONG_DETECT;

		return val & PORTC_HOTPLUG_LONG_DETECT;

	case PORT_D:

		return val & PORTD_HOTPLUG_LONG_DETECT;

	default:

	default:

		return false;

		return false;

	}

	}
@@ -2128,8 +2126,8 @@ static void bxt_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger, 
	struct drm_i915_private *dev_priv = to_i915(dev);

	struct drm_i915_private *dev_priv = to_i915(dev);

	u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;

	u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;





	dig_hotplug_reg = I915_READ(BXT_HOTPLUG_CTL);

	dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);

	I915_WRITE(BXT_HOTPLUG_CTL, dig_hotplug_reg);

	I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);





	intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,

	intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,

			   dig_hotplug_reg, hpd,

			   dig_hotplug_reg, hpd,
@@ -3247,27 +3245,17 @@ static void ilk_hpd_irq_setup(struct drm_device *dev) 
static void bxt_hpd_irq_setup(struct drm_device *dev)

static void bxt_hpd_irq_setup(struct drm_device *dev)

{

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 hotplug_port;

	u32 hotplug_irqs, hotplug, enabled_irqs;

	u32 hotplug_ctrl;



	hotplug_port = intel_hpd_enabled_irqs(dev, hpd_bxt);



	hotplug_ctrl = I915_READ(BXT_HOTPLUG_CTL) & ~BXT_HOTPLUG_CTL_MASK;





	if (hotplug_port & BXT_DE_PORT_HP_DDIA)

	enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bxt);

		hotplug_ctrl |= BXT_DDIA_HPD_ENABLE;

	hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;

	if (hotplug_port & BXT_DE_PORT_HP_DDIB)

		hotplug_ctrl |= BXT_DDIB_HPD_ENABLE;

	if (hotplug_port & BXT_DE_PORT_HP_DDIC)

		hotplug_ctrl |= BXT_DDIC_HPD_ENABLE;

	I915_WRITE(BXT_HOTPLUG_CTL, hotplug_ctrl);





	hotplug_ctrl = I915_READ(GEN8_DE_PORT_IMR) & ~hotplug_port;

	bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);

	I915_WRITE(GEN8_DE_PORT_IMR, hotplug_ctrl);





	hotplug_ctrl = I915_READ(GEN8_DE_PORT_IER) | hotplug_port;

	hotplug = I915_READ(PCH_PORT_HOTPLUG);

	I915_WRITE(GEN8_DE_PORT_IER, hotplug_ctrl);

	hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |

	POSTING_READ(GEN8_DE_PORT_IER);

		PORTA_HOTPLUG_ENABLE;

	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);

}

}





static void ibx_irq_postinstall(struct drm_device *dev)

static void ibx_irq_postinstall(struct drm_device *dev)
@@ -3561,7 +3549,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) 
					   GEN8_PIPE_FIFO_UNDERRUN;

					   GEN8_PIPE_FIFO_UNDERRUN;





	de_port_enables = de_port_masked;

	de_port_enables = de_port_masked;

	if (IS_BROADWELL(dev_priv))

	if (IS_BROXTON(dev_priv))

		de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;

	else if (IS_BROADWELL(dev_priv))

		de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;

		de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;





	dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;

	dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;

drivers/gpu/drm/i915/i915_reg.h

+0 −15
Original line number Original line Diff line number Diff line
@@ -5797,21 +5797,6 @@ enum skl_disp_power_wells { 
#define GEN8_PCU_IIR 0x444e8

#define GEN8_PCU_IIR 0x444e8

#define GEN8_PCU_IER 0x444ec

#define GEN8_PCU_IER 0x444ec





/* BXT hotplug control */

#define BXT_HOTPLUG_CTL			0xC4030

#define   BXT_DDIA_HPD_ENABLE		(1 << 28)

#define   BXT_DDIA_HPD_STATUS		(3 << 24)

#define   BXT_DDIC_HPD_ENABLE		(1 << 12)

#define   BXT_DDIC_HPD_STATUS		(3 << 8)

#define   BXT_DDIB_HPD_ENABLE		(1 << 4)

#define   BXT_DDIB_HPD_STATUS		(3 << 0)

#define   BXT_HOTPLUG_CTL_MASK		(BXT_DDIA_HPD_ENABLE | \

					 BXT_DDIB_HPD_ENABLE | \

					 BXT_DDIC_HPD_ENABLE)

#define   BXT_HPD_STATUS_MASK		(BXT_DDIA_HPD_STATUS | \

					 BXT_DDIB_HPD_STATUS | \

					 BXT_DDIC_HPD_STATUS)



#define ILK_DISPLAY_CHICKEN2	0x42004

#define ILK_DISPLAY_CHICKEN2	0x42004

/* Required on all Ironlake and Sandybridge according to the B-Spec. */

/* Required on all Ironlake and Sandybridge according to the B-Spec. */

#define  ILK_ELPIN_409_SELECT	(1 << 25)

#define  ILK_ELPIN_409_SELECT	(1 << 25)