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Commit a4eff487 authored by Stany MARCEL's avatar Stany MARCEL Committed by Greg Ungerer
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m68k: Set ColdFire ACR1 cache mode depending on kernel configuration 



For coldfire with MMU enabled, data cache did not follow the configuration but
was configured in writethrough mode.

Signed-off-by: default avatarStany MARCEL <stany.marcel@novasys-ingenierie.com>
Signed-off-by: default avatarGreg Ungerer <gerg@uclinux.org>
parent e4ba4fc2

arch/m68k/include/asm/m54xxacr.h

+6 −1
Original line number Diff line number Diff line
@@ -96,8 +96,13 @@ 
 */

#define ACR0_MODE	(ACR_BA(CONFIG_MBAR)+ACR_ADMSK(0x1000000)+ \

			 ACR_ENABLE+ACR_SUPER+ACR_CM_OFF_PRE+ACR_SP)

#if defined(CONFIG_CACHE_COPYBACK)

#define ACR1_MODE	(ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \

			 ACR_ENABLE+ACR_SUPER+ACR_SP)

			 ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_CP)

#else

#define ACR1_MODE	(ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \

			 ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_WT)

#endif

#define ACR2_MODE	0

#define ACR3_MODE	(ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \

			 ACR_ENABLE+ACR_SUPER+ACR_SP)