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Commit a4d4bbf1 authored by Alexandre Courbot's avatar Alexandre Courbot Committed by Ben Skeggs
Browse files

drm/nouveau/graph: add GK20A support 



Add a GR device for GK20A based on NVE4, with the correct classes
definitions (GK20A's 3D class is 0xa297).

Most of the NVE4 code can be used on GK20A, so make relevant bits of
NVE4 available to other chips as well.

Signed-off-by: default avatarAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 370eec76

drivers/gpu/drm/nouveau/Makefile

+2 −0
Original line number Original line Diff line number Diff line
@@ -259,6 +259,7 @@ nouveau-y += core/engine/graph/ctxnvc8.o 
nouveau-y += core/engine/graph/ctxnvd7.o

nouveau-y += core/engine/graph/ctxnvd7.o

nouveau-y += core/engine/graph/ctxnvd9.o

nouveau-y += core/engine/graph/ctxnvd9.o

nouveau-y += core/engine/graph/ctxnve4.o

nouveau-y += core/engine/graph/ctxnve4.o

nouveau-y += core/engine/graph/ctxgk20a.o

nouveau-y += core/engine/graph/ctxnvf0.o

nouveau-y += core/engine/graph/ctxnvf0.o

nouveau-y += core/engine/graph/ctxnv108.o

nouveau-y += core/engine/graph/ctxnv108.o

nouveau-y += core/engine/graph/ctxgm107.o

nouveau-y += core/engine/graph/ctxgm107.o
@@ -279,6 +280,7 @@ nouveau-y += core/engine/graph/nvc8.o 
nouveau-y += core/engine/graph/nvd7.o

nouveau-y += core/engine/graph/nvd7.o

nouveau-y += core/engine/graph/nvd9.o

nouveau-y += core/engine/graph/nvd9.o

nouveau-y += core/engine/graph/nve4.o

nouveau-y += core/engine/graph/nve4.o

nouveau-y += core/engine/graph/gk20a.o

nouveau-y += core/engine/graph/nvf0.o

nouveau-y += core/engine/graph/nvf0.o

nouveau-y += core/engine/graph/nv108.o

nouveau-y += core/engine/graph/nv108.o

nouveau-y += core/engine/graph/gm107.o

nouveau-y += core/engine/graph/gm107.o

drivers/gpu/drm/nouveau/core/engine/graph/ctxgk20a.c

0 → 100644
+53 −0
Original line number Original line Diff line number Diff line 
/*

 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

 * DEALINGS IN THE SOFTWARE.

 */



#include "ctxnvc0.h"



static const struct nvc0_graph_pack

gk20a_grctx_pack_mthd[] = {

	{ nve4_grctx_init_a097_0, 0xa297 },

	{ nvc0_grctx_init_902d_0, 0x902d },

	{}

};



struct nouveau_oclass *

gk20a_grctx_oclass = &(struct nvc0_grctx_oclass) {

	.base.handle = NV_ENGCTX(GR, 0xea),

	.base.ofuncs = &(struct nouveau_ofuncs) {

		.ctor = nvc0_graph_context_ctor,

		.dtor = nvc0_graph_context_dtor,

		.init = _nouveau_graph_context_init,

		.fini = _nouveau_graph_context_fini,

		.rd32 = _nouveau_graph_context_rd32,

		.wr32 = _nouveau_graph_context_wr32,

	},

	.main  = nve4_grctx_generate_main,

	.mods  = nve4_grctx_generate_mods,

	.unkn  = nve4_grctx_generate_unkn,

	.hub   = nve4_grctx_pack_hub,

	.gpc   = nve4_grctx_pack_gpc,

	.zcull = nvc0_grctx_pack_zcull,

	.tpc   = nve4_grctx_pack_tpc,

	.ppc   = nve4_grctx_pack_ppc,

	.icmd  = nve4_grctx_pack_icmd,

	.mthd  = gk20a_grctx_pack_mthd,

}.base;

drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.h

+9 −0
Original line number Original line Diff line number Diff line
@@ -69,7 +69,9 @@ extern struct nouveau_oclass *nvd7_grctx_oclass; 
extern struct nouveau_oclass *nvd9_grctx_oclass;

extern struct nouveau_oclass *nvd9_grctx_oclass;





extern struct nouveau_oclass *nve4_grctx_oclass;

extern struct nouveau_oclass *nve4_grctx_oclass;

extern struct nouveau_oclass *gk20a_grctx_oclass;

void nve4_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *);

void nve4_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *);

void nve4_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *);

void nve4_grctx_generate_unkn(struct nvc0_graph_priv *);

void nve4_grctx_generate_unkn(struct nvc0_graph_priv *);

void nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *);

void nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *);
@@ -151,6 +153,13 @@ extern const struct nvc0_graph_init nve4_grctx_init_gpm_0[]; 




extern const struct nvc0_graph_init nve4_grctx_init_pes_0[];

extern const struct nvc0_graph_init nve4_grctx_init_pes_0[];





extern const struct nvc0_graph_pack nve4_grctx_pack_hub[];

extern const struct nvc0_graph_pack nve4_grctx_pack_gpc[];

extern const struct nvc0_graph_pack nve4_grctx_pack_tpc[];

extern const struct nvc0_graph_pack nve4_grctx_pack_ppc[];

extern const struct nvc0_graph_pack nve4_grctx_pack_icmd[];

extern const struct nvc0_graph_init nve4_grctx_init_a097_0[];



extern const struct nvc0_graph_pack nvf0_grctx_pack_mthd[];

extern const struct nvc0_graph_pack nvf0_grctx_pack_mthd[];





extern const struct nvc0_graph_init nvf0_grctx_init_pri_0[];

extern const struct nvc0_graph_init nvf0_grctx_init_pri_0[];

drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c

+7 −7
Original line number Original line Diff line number Diff line
@@ -272,13 +272,13 @@ nve4_grctx_init_icmd_0[] = { 
	{}

	{}

};

};





static const struct nvc0_graph_pack

const struct nvc0_graph_pack

nve4_grctx_pack_icmd[] = {

nve4_grctx_pack_icmd[] = {

	{ nve4_grctx_init_icmd_0 },

	{ nve4_grctx_init_icmd_0 },

	{}

	{}

};

};





static const struct nvc0_graph_init

const struct nvc0_graph_init

nve4_grctx_init_a097_0[] = {

nve4_grctx_init_a097_0[] = {

	{ 0x000800,   8, 0x40, 0x00000000 },

	{ 0x000800,   8, 0x40, 0x00000000 },

	{ 0x000804,   8, 0x40, 0x00000000 },

	{ 0x000804,   8, 0x40, 0x00000000 },
@@ -697,7 +697,7 @@ nve4_grctx_init_be_0[] = { 
	{}

	{}

};

};





static const struct nvc0_graph_pack

const struct nvc0_graph_pack

nve4_grctx_pack_hub[] = {

nve4_grctx_pack_hub[] = {

	{ nvc0_grctx_init_main_0 },

	{ nvc0_grctx_init_main_0 },

	{ nve4_grctx_init_fe_0 },

	{ nve4_grctx_init_fe_0 },
@@ -737,7 +737,7 @@ nve4_grctx_init_gpm_0[] = { 
	{}

	{}

};

};





static const struct nvc0_graph_pack

const struct nvc0_graph_pack

nve4_grctx_pack_gpc[] = {

nve4_grctx_pack_gpc[] = {

	{ nvc0_grctx_init_gpc_unk_0 },

	{ nvc0_grctx_init_gpc_unk_0 },

	{ nvd9_grctx_init_prop_0 },

	{ nvd9_grctx_init_prop_0 },
@@ -802,7 +802,7 @@ nve4_grctx_init_sm_0[] = { 
	{}

	{}

};

};





static const struct nvc0_graph_pack

const struct nvc0_graph_pack

nve4_grctx_pack_tpc[] = {

nve4_grctx_pack_tpc[] = {

	{ nvd7_grctx_init_pe_0 },

	{ nvd7_grctx_init_pe_0 },

	{ nve4_grctx_init_tex_0 },

	{ nve4_grctx_init_tex_0 },
@@ -826,7 +826,7 @@ nve4_grctx_init_cbm_0[] = { 
	{}

	{}

};

};





static const struct nvc0_graph_pack

const struct nvc0_graph_pack

nve4_grctx_pack_ppc[] = {

nve4_grctx_pack_ppc[] = {

	{ nve4_grctx_init_pes_0 },

	{ nve4_grctx_init_pes_0 },

	{ nve4_grctx_init_cbm_0 },

	{ nve4_grctx_init_cbm_0 },
@@ -838,7 +838,7 @@ nve4_grctx_pack_ppc[] = { 
 * PGRAPH context implementation

 * PGRAPH context implementation

 ******************************************************************************/

 ******************************************************************************/





static void

void

nve4_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)

nve4_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)

{

{

	u32 magic[GPC_MAX][2];

	u32 magic[GPC_MAX][2];

drivers/gpu/drm/nouveau/core/engine/graph/gk20a.c

0 → 100644
+47 −0
Original line number Original line Diff line number Diff line 
/*

 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

 * DEALINGS IN THE SOFTWARE.

 */



#include "nvc0.h"

#include "ctxnvc0.h"



static struct nouveau_oclass

gk20a_graph_sclass[] = {

	{ 0x902d, &nouveau_object_ofuncs },

	{ 0xa040, &nouveau_object_ofuncs },

	{ 0xa297, &nouveau_object_ofuncs },

	{ 0xa0c0, &nouveau_object_ofuncs },

	{}

};



struct nouveau_oclass *

gk20a_graph_oclass = &(struct nvc0_graph_oclass) {

	.base.handle = NV_ENGINE(GR, 0xea),

	.base.ofuncs = &(struct nouveau_ofuncs) {

		.ctor = nvc0_graph_ctor,

		.dtor = nvc0_graph_dtor,

		.init = nve4_graph_init,

		.fini = nve4_graph_fini,

	},

	.cclass = &gk20a_grctx_oclass,

	.sclass = gk20a_graph_sclass,

	.mmio = nve4_graph_pack_mmio,

}.base;