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Commit a4565da8 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915/chv: Initial clock gating support for Cherryview 



CHV clock gating isn't identical to VLV, so add a new function
for it. This is only a start, and further changes are needed as
the details become available.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 74e1ca8c

drivers/gpu/drm/i915/intel_pm.c

+13 −0
Original line number Diff line number Diff line
@@ -5335,6 +5335,15 @@ static void valleyview_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);

}



static void cherryview_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);



	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);

}



static void g4x_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6270,6 +6279,10 @@ void intel_init_pm(struct drm_device *dev) 
			dev_priv->display.init_clock_gating = haswell_init_clock_gating;

		else if (INTEL_INFO(dev)->gen == 8)

			dev_priv->display.init_clock_gating = gen8_init_clock_gating;

	} else if (IS_CHERRYVIEW(dev)) {

		dev_priv->display.update_wm = valleyview_update_wm;

		dev_priv->display.init_clock_gating =

			cherryview_init_clock_gating;

	} else if (IS_VALLEYVIEW(dev)) {

		dev_priv->display.update_wm = valleyview_update_wm;

		dev_priv->display.init_clock_gating =