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Commit a3df6f7d authored by Paul Mackerras's avatar Paul Mackerras Committed by Ingo Molnar
Browse files

perf_counter/powerpc: Fix cache event codes for POWER7 



I had the codes for L1 D-cache load accesses and misses swapped
around, and the wrong codes for LL-cache accesses and misses.
This corrects them.

Reported-by: default avatarCorey Ashford <cjashfor@linux.vnet.ibm.com>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: <stable@kernel.org>
LKML-Reference: <19103.8514.709300.585484@cargo.ozlabs.ibm.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent eced1dfc

arch/powerpc/kernel/power7-pmu.c

+3 −3
Original line number Diff line number Diff line
@@ -317,7 +317,7 @@ static int power7_generic_events[] = { 
 */

static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {

	[C(L1D)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

		[C(OP_READ)] = {	0x400f0,	0xc880	},

		[C(OP_READ)] = {	0xc880,		0x400f0	},

		[C(OP_WRITE)] = {	0,		0x300f0	},

		[C(OP_PREFETCH)] = {	0xd8b8,		0	},

	},
@@ -327,8 +327,8 @@ static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { 
		[C(OP_PREFETCH)] = {	0x408a,		0	},

	},

	[C(LL)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

		[C(OP_READ)] = {	0x6080,		0x6084	},

		[C(OP_WRITE)] = {	0x6082,		0x6086	},

		[C(OP_READ)] = {	0x16080,	0x26080	},

		[C(OP_WRITE)] = {	0x16082,	0x26082	},

		[C(OP_PREFETCH)] = {	0,		0	},

	},

	[C(DTLB)] = {		/* 	RESULT_ACCESS	RESULT_MISS */