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Commit a3228bc8 authored by Ian Abbott's avatar Ian Abbott Committed by Greg Kroah-Hartman
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staging: comedi: drivers: re-do PLX PCI 9080 CNTRL register values 



Replace the existing macros in "plx9080.h" that define values for the
CNTRL register.  Use the prefix `PLX_CNTRL_` for the macros.  Make use
of the `BIT(x)` and `GENMASK(h,l)` macros to define the values.

Signed-off-by: default avatarIan Abbott <abbotti@mev.co.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 9dc53852

drivers/staging/comedi/drivers/cb_pcidas64.c

+16 −15
Original line number Diff line number Diff line
@@ -1614,7 +1614,7 @@ static const int i2c_low_udelay = 10; 
static void i2c_set_sda(struct comedi_device *dev, int state)

{

	struct pcidas64_private *devpriv = dev->private;

	static const int data_bit = CTL_EE_W;

	static const int data_bit = PLX_CNTRL_EEWB;

	void __iomem *plx_control_addr = devpriv->plx9080_iobase +

					 PLX_REG_CNTRL;
@@ -1635,7 +1635,7 @@ static void i2c_set_sda(struct comedi_device *dev, int state) 
static void i2c_set_scl(struct comedi_device *dev, int state)

{

	struct pcidas64_private *devpriv = dev->private;

	static const int clock_bit = CTL_USERO;

	static const int clock_bit = PLX_CNTRL_USERO;

	void __iomem *plx_control_addr = devpriv->plx9080_iobase +

					 PLX_REG_CNTRL;
@@ -1708,7 +1708,7 @@ static void i2c_write(struct comedi_device *dev, unsigned int address, 
	 */



	/*  make sure we dont send anything to eeprom */

	devpriv->plx_control_bits &= ~CTL_EE_CS;

	devpriv->plx_control_bits &= ~PLX_CNTRL_EECS;



	i2c_stop(dev);

	i2c_start(dev);
@@ -3717,13 +3717,13 @@ static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address) 
	static const int eeprom_udelay = 1;



	udelay(eeprom_udelay);

	devpriv->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS;

	devpriv->plx_control_bits &= ~PLX_CNTRL_EESK & ~PLX_CNTRL_EECS;

	/*  make sure we don't send anything to the i2c bus on 4020 */

	devpriv->plx_control_bits |= CTL_USERO;

	devpriv->plx_control_bits |= PLX_CNTRL_USERO;

	writel(devpriv->plx_control_bits, plx_control_addr);

	/*  activate serial eeprom */

	udelay(eeprom_udelay);

	devpriv->plx_control_bits |= CTL_EE_CS;

	devpriv->plx_control_bits |= PLX_CNTRL_EECS;

	writel(devpriv->plx_control_bits, plx_control_addr);



	/*  write read command and desired memory address */
@@ -3731,16 +3731,16 @@ static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address) 
		/*  set bit to be written */

		udelay(eeprom_udelay);

		if (bitstream & bit)

			devpriv->plx_control_bits |= CTL_EE_W;

			devpriv->plx_control_bits |= PLX_CNTRL_EEWB;

		else

			devpriv->plx_control_bits &= ~CTL_EE_W;

			devpriv->plx_control_bits &= ~PLX_CNTRL_EEWB;

		writel(devpriv->plx_control_bits, plx_control_addr);

		/*  clock in bit */

		udelay(eeprom_udelay);

		devpriv->plx_control_bits |= CTL_EE_CLK;

		devpriv->plx_control_bits |= PLX_CNTRL_EESK;

		writel(devpriv->plx_control_bits, plx_control_addr);

		udelay(eeprom_udelay);

		devpriv->plx_control_bits &= ~CTL_EE_CLK;

		devpriv->plx_control_bits &= ~PLX_CNTRL_EESK;

		writel(devpriv->plx_control_bits, plx_control_addr);

	}

	/*  read back value from eeprom memory location */
@@ -3748,19 +3748,19 @@ static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address) 
	for (bit = 1 << (value_length - 1); bit; bit >>= 1) {

		/*  clock out bit */

		udelay(eeprom_udelay);

		devpriv->plx_control_bits |= CTL_EE_CLK;

		devpriv->plx_control_bits |= PLX_CNTRL_EESK;

		writel(devpriv->plx_control_bits, plx_control_addr);

		udelay(eeprom_udelay);

		devpriv->plx_control_bits &= ~CTL_EE_CLK;

		devpriv->plx_control_bits &= ~PLX_CNTRL_EESK;

		writel(devpriv->plx_control_bits, plx_control_addr);

		udelay(eeprom_udelay);

		if (readl(plx_control_addr) & CTL_EE_R)

		if (readl(plx_control_addr) & PLX_CNTRL_EERB)

			value |= bit;

	}



	/*  deactivate eeprom serial input */

	udelay(eeprom_udelay);

	devpriv->plx_control_bits &= ~CTL_EE_CS;

	devpriv->plx_control_bits &= ~PLX_CNTRL_EECS;

	writel(devpriv->plx_control_bits, plx_control_addr);



	return value;
@@ -3948,7 +3948,8 @@ static int setup_subdevices(struct comedi_device *dev) 


	/* serial EEPROM, if present */

	s = &dev->subdevices[8];

	if (readl(devpriv->plx9080_iobase + PLX_REG_CNTRL) & CTL_EECHK) {

	if (readl(devpriv->plx9080_iobase + PLX_REG_CNTRL) &

	    PLX_CNTRL_EEPRESENT) {

		s->type = COMEDI_SUBD_MEMORY;

		s->subdev_flags = SDF_READABLE | SDF_INTERNAL;

		s->n_chan = 128;

drivers/staging/comedi/drivers/plx9080.h

+49 −14
Original line number Diff line number Diff line
@@ -393,20 +393,55 @@ struct plx_dma_desc { 
 */

#define PLX_REG_CNTRL		0x006c



#define  CTL_RDMA          0x0000000E	/* DMA Read Command */

#define  CTL_WDMA          0x00000070	/* DMA Write Command */

#define  CTL_RMEM          0x00000600	/* Memory Read Command */

#define  CTL_WMEM          0x00007000	/* Memory Write Command */

#define  CTL_USERO         0x00010000	/* USERO output pin control bit */

#define  CTL_USERI         0x00020000	/* USERI input pin bit */

#define  CTL_EE_CLK        0x01000000	/* EEPROM Clock line */

#define  CTL_EE_CS         0x02000000	/* EEPROM Chip Select */

#define  CTL_EE_W          0x04000000	/* EEPROM Write bit */

#define  CTL_EE_R          0x08000000	/* EEPROM Read bit */

#define  CTL_EECHK         0x10000000	/* EEPROM Present bit */

#define  CTL_EERLD         0x20000000	/* EEPROM Reload Register */

#define  CTL_RESET         0x40000000	/* !! Adapter Reset !! */

#define  CTL_READY         0x80000000	/* Local Init Done */

/* PCI Read Command Code For DMA */

#define PLX_CNTRL_CCRDMA(x)	(BIT(0) * ((x) & 0xf))

#define PLX_CNTRL_CCRDMA_MASK	GENMASK(3, 0)

#define PLX_CNTRL_CCRDMA_SHIFT	0

#define PLX_CNTRL_CCRDMA_NORMAL	PLX_CNTRL_CCRDMA(14)	/* value after reset */

/* PCI Write Command Code For DMA 0 */

#define PLX_CNTRL_CCWDMA(x)	(BIT(4) * ((x) & 0xf))

#define PLX_CNTRL_CCWDMA_MASK	GENMASK(7, 4)

#define PLX_CNTRL_CCWDMA_SHIFT	4

#define PLX_CNTRL_CCWDMA_NORMAL	PLX_CNTRL_CCWDMA(7)	/* value after reset */

/* PCI Memory Read Command Code For Direct Master */

#define PLX_CNTRL_CCRDM(x)	(BIT(8) * ((x) & 0xf))

#define PLX_CNTRL_CCRDM_MASK	GENMASK(11, 8)

#define PLX_CNTRL_CCRDM_SHIFT	8

#define PLX_CNTRL_CCRDM_NORMAL	PLX_CNTRL_CCRDM(6)	/* value after reset */

/* PCI Memory Write Command Code For Direct Master */

#define PLX_CNTRL_CCWDM(x)	(BIT(12) * ((x) & 0xf))

#define PLX_CNTRL_CCWDM_MASK	GENMASK(15, 12)

#define PLX_CNTRL_CCWDM_SHIFT	12

#define PLX_CNTRL_CCWDM_NORMAL	PLX_CNTRL_CCWDM(7)	/* value after reset */

/* General Purpose Output (USERO) */

#define PLX_CNTRL_USERO		BIT(16)

/* General Purpose Input (USERI) (read-only) */

#define PLX_CNTRL_USERI		BIT(17)

/* Serial EEPROM Clock Output (EESK) */

#define PLX_CNTRL_EESK		BIT(24)

/* Serial EEPROM Chip Select Output (EECS) */

#define PLX_CNTRL_EECS		BIT(25)

/* Serial EEPROM Data Write Bit (EEDI (sic)) */

#define PLX_CNTRL_EEWB		BIT(26)

/* Serial EEPROM Data Read Bit (EEDO (sic)) (read-only) */

#define PLX_CNTRL_EERB		BIT(27)

/* Serial EEPROM Present (read-only) */

#define PLX_CNTRL_EEPRESENT	BIT(28)

/* Reload Configuration Registers from EEPROM */

#define PLX_CNTRL_EERELOAD	BIT(29)

/* PCI Adapter Software Reset (asserts LRESETo#) */

#define PLX_CNTRL_RESET		BIT(30)

/* Local Init Status (read-only) */

#define PLX_CNTRL_INITDONE	BIT(31)

/*

 * Combined command code stuff for convenience.

 */

#define PLX_CNTRL_CC_MASK	\

	(PLX_CNTRL_CCRDMA_MASK | PLX_CNTRL_CCWDMA_MASK | \

	 PLX_CNTRL_CCRDM_MASK | PLX_CNTRL_CCWDM_MASK)

#define PLX_CNTRL_CC_NORMAL	\

	(PLX_CNTRL_CCRDMA_NORMAL | PLX_CNTRL_CCWDMA_NORMAL | \

	 PLX_CNTRL_CCRDM_NORMAL | PLX_CNTRL_CCWDM_NORMAL) /* val after reset */



/* PCI Permanent Configuration ID Register (hard-coded PLX vendor and device) */

#define PLX_REG_PCIHIDR		0x0070