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Commit a319726a authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-next

parents 62ecc379 8e2813f5

drivers/net/ethernet/intel/e1000e/80003es2lan.c

+8 −0
Original line number Diff line number Diff line
@@ -764,6 +764,7 @@ static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) 
{

	u32 ctrl;

	s32 ret_val;

	u16 kum_reg_data;



	/*

	 * Prevent the PCI-E bus from sticking if there is no TLP connection
@@ -789,6 +790,13 @@ static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) 
	ew32(CTRL, ctrl | E1000_CTRL_RST);

	e1000_release_phy_80003es2lan(hw);



	/* Disable IBIST slave mode (far-end loopback) */

	e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,

					&kum_reg_data);

	kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;

	e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,

					 kum_reg_data);



	ret_val = e1000e_get_auto_rd_done(hw);

	if (ret_val)

		/* We don't want to continue accessing MAC registers. */

drivers/net/ethernet/intel/e1000e/82571.c

+2 −1
Original line number Diff line number Diff line
@@ -2062,7 +2062,8 @@ const struct e1000_info e1000_82574_info = { 
				  | FLAG_HAS_CTRLEXT_ON_LOAD,

	.flags2			  = FLAG2_CHECK_PHY_HANG

				  | FLAG2_DISABLE_ASPM_L0S

				  | FLAG2_NO_DISABLE_RX,

				  | FLAG2_NO_DISABLE_RX

				  | FLAG2_DMA_BURST,

	.pba			= 32,

	.max_hw_frame_size	= DEFAULT_JUMBO,

	.get_variants		= e1000_get_variants_82571,

drivers/net/ethernet/intel/e1000e/e1000.h

+37 −0
Original line number Diff line number Diff line
@@ -735,9 +735,46 @@ static inline u32 __er32(struct e1000_hw *hw, unsigned long reg) 
	return readl(hw->hw_addr + reg);

}



#define er32(reg)	__er32(hw, E1000_##reg)



/**

 * __ew32_prepare - prepare to write to MAC CSR register on certain parts

 * @hw: pointer to the HW structure

 *

 * When updating the MAC CSR registers, the Manageability Engine (ME) could

 * be accessing the registers at the same time.  Normally, this is handled in

 * h/w by an arbiter but on some parts there is a bug that acknowledges Host

 * accesses later than it should which could result in the register to have

 * an incorrect value.  Workaround this by checking the FWSM register which

 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set

 * and try again a number of times.

 **/

static inline s32 __ew32_prepare(struct e1000_hw *hw)

{

	s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;



	while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)

		udelay(50);



	return i;

}



static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)

{

	if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)

		__ew32_prepare(hw);



	writel(val, hw->hw_addr + reg);

}



#define ew32(reg, val)	__ew32(hw, E1000_##reg, (val))



#define e1e_flush()	er32(STATUS)



#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \

	(__ew32((a), (reg + ((offset) << 2)), (value)))



#define E1000_READ_REG_ARRAY(a, reg, offset) \

	(readl((a)->hw_addr + reg + ((offset) << 2)))



#endif /* _E1000_H_ */

drivers/net/ethernet/intel/e1000e/hw.h

+0 −10
Original line number Diff line number Diff line
@@ -36,16 +36,6 @@ struct e1000_adapter; 


#include "defines.h"



#define er32(reg)	__er32(hw, E1000_##reg)

#define ew32(reg,val)	__ew32(hw, E1000_##reg, (val))

#define e1e_flush()	er32(STATUS)



#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \

	(writel((value), ((a)->hw_addr + reg + ((offset) << 2))))



#define E1000_READ_REG_ARRAY(a, reg, offset) \

	(readl((a)->hw_addr + reg + ((offset) << 2)))



enum e1e_registers {

	E1000_CTRL     = 0x00000, /* Device Control - RW */

	E1000_STATUS   = 0x00008, /* Device Status - RO */

drivers/net/ethernet/intel/e1000e/ich8lan.c

+11 −0
Original line number Diff line number Diff line
@@ -135,6 +135,7 @@ 


/* PHY Power Management Control */

#define HV_PM_CTRL		PHY_REG(770, 17)

#define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA	0x100



/* PHY Low Power Idle Control */

#define I82579_LPI_CTRL				PHY_REG(772, 20)
@@ -1708,8 +1709,18 @@ static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) 
			return ret_val;



		if (status_reg & HV_M_STATUS_SPEED_1000) {

			u16 pm_phy_reg;



			mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;

			phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;

			/* LV 1G Packet drop issue wa  */

			ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);

			if (ret_val)

				return ret_val;

			pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA;

			ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);

			if (ret_val)

				return ret_val;

		} else {

			mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;

			phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;