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Commit a2f4c560 authored by Chris Zhong's avatar Chris Zhong Committed by Heiko Stuebner
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clk: rockchip: add mipidsi clock on rk3288 



sclk_mipidsi_24m is the gating of mipi dsi phy.

Signed-off-by: default avatarChris Zhong <zyw@rock-chips.com>
Acked-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 25286bef

drivers/clk/rockchip/clk-rk3288.c

+1 −1
Original line number Diff line number Diff line
@@ -709,7 +709,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { 
	GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS),

	GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS),

	GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS),

	GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS),

	GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS),



	/* sclk_gpu gates */

	GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 0, RK3288_CLKGATE_CON(18), 0, GFLAGS),