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Commit a2cce7a9 authored by Bhupesh Sharma's avatar Bhupesh Sharma Committed by Arnd Bergmann
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Documentation/dts: Move FSL board-specific bindings out of /powerpc 



Since the same board components can be used across ARM and PPC board families,
this patch moves the FSL board-specific bindings out of bindings/powerpci.

While at it, this patch also adds the bindings for QIXIS FPGA controller
found on FSL LS2080A boards. These boards have an on-board FPGA/CPLD
connected to the IFC controller.

Signed-off-by: default avatarBhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: default avatarJaiprakash Singh <b44839@freescale.com>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent cc56a128

Documentation/devicetree/bindings/powerpc/fsl/board.txt→Documentation/devicetree/bindings/board/fsl-board.txt

+12 −2
Original line number Diff line number Diff line
@@ -21,11 +21,14 @@ Example: 


This is the memory-mapped registers for on board FPGA.



Required properities:

Required properties:

- compatible: should be a board-specific string followed by a string

  indicating the type of FPGA.  Example:

	"fsl,<board>-fpga", "fsl,fpga-pixis"

	"fsl,<board>-fpga", "fsl,fpga-pixis", or

	"fsl,<board>-fpga", "fsl,fpga-qixis"

- reg: should contain the address and the length of the FPGA register set.



Optional properties:

- interrupt-parent: should specify phandle for the interrupt controller.

- interrupts: should specify event (wakeup) IRQ.
@@ -38,6 +41,13 @@ Example (P1022DS): 
		 interrupts = <8 8 0 0>;

	 };



Example (LS2080A-RDB):



        cpld@3,0 {

                compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis";

                reg = <0x3 0 0x10000>;

        };



* Freescale BCSR GPIO banks



Some BCSR registers act as simple GPIO controllers, each such