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Commit a26bce12 authored by Will Deacon's avatar Will Deacon Committed by Russell King
Browse files

ARM: 7127/1: hw_breakpoint: skip v7-specific reset on v6 cores 



ARMv6 cores do not implement the DBGOSLAR register, so we don't need to
try and clear it on boot. Furthermore, the VCR is zeroed out of reset,
so we don't need to zero it explicitly when a CPU comes online.

Tested-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent c825dda9

arch/arm/kernel/hw_breakpoint.c

+5 −0
Original line number Diff line number Diff line
@@ -892,6 +892,10 @@ static void reset_ctrl_regs(void *unused) 
	 * later on.

	 */

	switch (debug_arch) {

	case ARM_DEBUG_ARCH_V6:

	case ARM_DEBUG_ARCH_V6_1:

		/* ARMv6 cores just need to reset the registers. */

		goto reset_regs;

	case ARM_DEBUG_ARCH_V7_ECP14:

		/*

		 * Ensure sticky power-down is clear (i.e. debug logic is
@@ -931,6 +935,7 @@ static void reset_ctrl_regs(void *unused) 
	asm volatile("mcr p14, 0, %0, c0, c7, 0" : : "r" (0));

	isb();



reset_regs:

	if (enable_monitor_mode())

		return;