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Commit a23eefa2 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/powerplay: enable dpm for baffin. 



Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c8172625

drivers/gpu/drm/amd/powerplay/hwmgr/Makefile

+2 −1
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@@ -8,7 +8,8 @@ HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \ 
	       tonga_processpptables.o ppatomctrl.o \

               tonga_hwmgr.o pppcielanes.o  tonga_thermal.o\

               fiji_powertune.o fiji_hwmgr.o tonga_clockpowergating.o \

               fiji_clockpowergating.o fiji_thermal.o

               fiji_clockpowergating.o fiji_thermal.o \

	       ellesmere_hwmgr.o ellesmere_powertune.o



AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))

drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_dyn_defaults.h

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/*

 * Copyright 2015 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#ifndef ELLESMERE_DYN_DEFAULTS_H

#define ELLESMERE_DYN_DEFAULTS_H





enum Ellesmeredpm_TrendDetection {

	EllesmereAdpm_TrendDetection_AUTO,

	EllesmereAdpm_TrendDetection_UP,

	EllesmereAdpm_TrendDetection_DOWN

};

typedef enum Ellesmeredpm_TrendDetection Ellesmeredpm_TrendDetection;



/*  We need to fill in the default values */





#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT0              0x3FFFC102

#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT1              0x000400

#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT2              0xC00080

#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT3              0xC00200

#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT4              0xC01680

#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT5              0xC00033

#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT6              0xC00033

#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT7              0x3FFFC000





#define PPELLESMERE_THERMALPROTECTCOUNTER_DFLT            0x200

#define PPELLESMERE_STATICSCREENTHRESHOLDUNIT_DFLT        0

#define PPELLESMERE_STATICSCREENTHRESHOLD_DFLT            0x00C8

#define PPELLESMERE_GFXIDLECLOCKSTOPTHRESHOLD_DFLT        0x200

#define PPELLESMERE_REFERENCEDIVIDER_DFLT                  4



#define PPELLESMERE_ULVVOLTAGECHANGEDELAY_DFLT             1687



#define PPELLESMERE_CGULVPARAMETER_DFLT                    0x00040035

#define PPELLESMERE_CGULVCONTROL_DFLT                      0x00007450

#define PPELLESMERE_TARGETACTIVITY_DFLT                     50

#define PPELLESMERE_MCLK_TARGETACTIVITY_DFLT                10



#endif

drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c

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drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h

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Original line number Diff line number Diff line 
/*

 * Copyright 2015 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#ifndef ELLESMERE_HWMGR_H

#define ELLESMERE_HWMGR_H



#include "hwmgr.h"

#include "smu74.h"

#include "smu74_discrete.h"

#include "ppatomctrl.h"

#include "ellesmere_ppsmc.h"

#include "ellesmere_powertune.h"



#define ELLESMERE_MAX_HARDWARE_POWERLEVELS	2



#define ELLESMERE_VOLTAGE_CONTROL_NONE                   0x0

#define ELLESMERE_VOLTAGE_CONTROL_BY_GPIO                0x1

#define ELLESMERE_VOLTAGE_CONTROL_BY_SVID2               0x2

#define ELLESMERE_VOLTAGE_CONTROL_MERGED                 0x3



#define DPMTABLE_OD_UPDATE_SCLK     0x00000001

#define DPMTABLE_OD_UPDATE_MCLK     0x00000002

#define DPMTABLE_UPDATE_SCLK        0x00000004

#define DPMTABLE_UPDATE_MCLK        0x00000008



struct ellesmere_performance_level {

	uint32_t  memory_clock;

	uint32_t  engine_clock;

	uint16_t  pcie_gen;

	uint16_t  pcie_lane;

};



struct ellesmere_uvd_clocks {

	uint32_t  vclk;

	uint32_t  dclk;

};



struct ellesmere_vce_clocks {

	uint32_t  evclk;

	uint32_t  ecclk;

};



struct ellesmere_power_state {

	uint32_t                  magic;

	struct ellesmere_uvd_clocks    uvd_clks;

	struct ellesmere_vce_clocks    vce_clks;

	uint32_t                  sam_clk;

	uint16_t                  performance_level_count;

	bool                      dc_compatible;

	uint32_t                  sclk_threshold;

	struct ellesmere_performance_level  performance_levels[ELLESMERE_MAX_HARDWARE_POWERLEVELS];

};



struct ellesmere_dpm_level {

	bool	enabled;

	uint32_t	value;

	uint32_t	param1;

};



#define ELLESMERE_MAX_DEEPSLEEP_DIVIDER_ID 5

#define MAX_REGULAR_DPM_NUMBER 8

#define ELLESMERE_MINIMUM_ENGINE_CLOCK 2500



struct ellesmere_single_dpm_table {

	uint32_t		count;

	struct ellesmere_dpm_level	dpm_levels[MAX_REGULAR_DPM_NUMBER];

};



struct ellesmere_dpm_table {

	struct ellesmere_single_dpm_table  sclk_table;

	struct ellesmere_single_dpm_table  mclk_table;

	struct ellesmere_single_dpm_table  pcie_speed_table;

	struct ellesmere_single_dpm_table  vddc_table;

	struct ellesmere_single_dpm_table  vddci_table;

	struct ellesmere_single_dpm_table  mvdd_table;

};



struct ellesmere_clock_registers {

	uint32_t  vCG_SPLL_FUNC_CNTL;

	uint32_t  vCG_SPLL_FUNC_CNTL_2;

	uint32_t  vCG_SPLL_FUNC_CNTL_3;

	uint32_t  vCG_SPLL_FUNC_CNTL_4;

	uint32_t  vCG_SPLL_SPREAD_SPECTRUM;

	uint32_t  vCG_SPLL_SPREAD_SPECTRUM_2;

	uint32_t  vDLL_CNTL;

	uint32_t  vMCLK_PWRMGT_CNTL;

	uint32_t  vMPLL_AD_FUNC_CNTL;

	uint32_t  vMPLL_DQ_FUNC_CNTL;

	uint32_t  vMPLL_FUNC_CNTL;

	uint32_t  vMPLL_FUNC_CNTL_1;

	uint32_t  vMPLL_FUNC_CNTL_2;

	uint32_t  vMPLL_SS1;

	uint32_t  vMPLL_SS2;

};



#define DISABLE_MC_LOADMICROCODE   1

#define DISABLE_MC_CFGPROGRAMMING  2



struct ellesmere_voltage_smio_registers {

	uint32_t vS0_VID_LOWER_SMIO_CNTL;

};



#define ELLESMERE_MAX_LEAKAGE_COUNT  8



struct ellesmere_leakage_voltage {

	uint16_t  count;

	uint16_t  leakage_id[ELLESMERE_MAX_LEAKAGE_COUNT];

	uint16_t  actual_voltage[ELLESMERE_MAX_LEAKAGE_COUNT];

};



struct ellesmere_vbios_boot_state {

	uint16_t    mvdd_bootup_value;

	uint16_t    vddc_bootup_value;

	uint16_t    vddci_bootup_value;

	uint32_t    sclk_bootup_value;

	uint32_t    mclk_bootup_value;

	uint16_t    pcie_gen_bootup_value;

	uint16_t    pcie_lane_bootup_value;

};



/* Ultra Low Voltage parameter structure */

struct ellesmere_ulv_parm {

	bool                           ulv_supported;

	uint32_t                       cg_ulv_parameter;

	uint32_t                       ulv_volt_change_delay;

	struct ellesmere_performance_level  ulv_power_level;

};



struct ellesmere_display_timing {

	uint32_t  min_clock_in_sr;

	uint32_t  num_existing_displays;

};



struct ellesmere_dpmlevel_enable_mask {

	uint32_t  uvd_dpm_enable_mask;

	uint32_t  vce_dpm_enable_mask;

	uint32_t  acp_dpm_enable_mask;

	uint32_t  samu_dpm_enable_mask;

	uint32_t  sclk_dpm_enable_mask;

	uint32_t  mclk_dpm_enable_mask;

	uint32_t  pcie_dpm_enable_mask;

};



struct ellesmere_pcie_perf_range {

	uint16_t  max;

	uint16_t  min;

};

struct ellesmere_range_table {

	uint32_t trans_lower_frequency; /* in 10khz */

	uint32_t trans_upper_frequency;

};



struct ellesmere_hwmgr {

	struct ellesmere_dpm_table			dpm_table;

	struct ellesmere_dpm_table			golden_dpm_table;

	SMU74_Discrete_DpmTable				smc_state_table;

	struct SMU74_Discrete_Ulv            ulv_setting;



	struct ellesmere_range_table                range_table[NUM_SCLK_RANGE];

	uint32_t						voting_rights_clients0;

	uint32_t						voting_rights_clients1;

	uint32_t						voting_rights_clients2;

	uint32_t						voting_rights_clients3;

	uint32_t						voting_rights_clients4;

	uint32_t						voting_rights_clients5;

	uint32_t						voting_rights_clients6;

	uint32_t						voting_rights_clients7;

	uint32_t						static_screen_threshold_unit;

	uint32_t						static_screen_threshold;

	uint32_t						voltage_control;

	uint32_t						vddc_vddci_delta;



	uint32_t						active_auto_throttle_sources;



	struct ellesmere_clock_registers            clock_registers;

	struct ellesmere_voltage_smio_registers      voltage_smio_registers;



	bool                           is_memory_gddr5;

	uint16_t                       acpi_vddc;

	bool                           pspp_notify_required;

	uint16_t                       force_pcie_gen;

	uint16_t                       acpi_pcie_gen;

	uint32_t                       pcie_gen_cap;

	uint32_t                       pcie_lane_cap;

	uint32_t                       pcie_spc_cap;

	struct ellesmere_leakage_voltage          vddc_leakage;

	struct ellesmere_leakage_voltage          Vddci_leakage;



	uint32_t                             mvdd_control;

	uint32_t                             vddc_mask_low;

	uint32_t                             mvdd_mask_low;

	uint16_t                            max_vddc_in_pptable;

	uint16_t                            min_vddc_in_pptable;

	uint16_t                            max_vddci_in_pptable;

	uint16_t                            min_vddci_in_pptable;

	uint32_t                             mclk_strobe_mode_threshold;

	uint32_t                             mclk_stutter_mode_threshold;

	uint32_t                             mclk_edc_enable_threshold;

	uint32_t                             mclk_edcwr_enable_threshold;

	bool                                is_uvd_enabled;

	struct ellesmere_vbios_boot_state        vbios_boot_state;



	bool                           pcie_performance_request;

	bool                           battery_state;

	bool                           is_tlu_enabled;



	/* ---- SMC SRAM Address of firmware header tables ---- */

	uint32_t                             sram_end;

	uint32_t                             dpm_table_start;

	uint32_t                             soft_regs_start;

	uint32_t                             mc_reg_table_start;

	uint32_t                             fan_table_start;

	uint32_t                             arb_table_start;



	/* ---- Stuff originally coming from Evergreen ---- */

	uint32_t                             vddci_control;

	struct pp_atomctrl_voltage_table     vddc_voltage_table;

	struct pp_atomctrl_voltage_table     vddci_voltage_table;

	struct pp_atomctrl_voltage_table     mvdd_voltage_table;



	uint32_t                             mgcg_cgtt_local2;

	uint32_t                             mgcg_cgtt_local3;

	uint32_t                             gpio_debug;

	uint32_t                             mc_micro_code_feature;

	uint32_t                             highest_mclk;

	uint16_t                             acpi_vddci;

	uint8_t                              mvdd_high_index;

	uint8_t                              mvdd_low_index;

	bool                                 dll_default_on;

	bool                                 performance_request_registered;



	/* ---- Low Power Features ---- */

	struct ellesmere_ulv_parm                 ulv;



	/* ---- CAC Stuff ---- */

	uint32_t                       cac_table_start;

	bool                           cac_configuration_required;

	bool                           driver_calculate_cac_leakage;

	bool                           cac_enabled;



	/* ---- DPM2 Parameters ---- */

	uint32_t                       power_containment_features;

	bool                           enable_dte_feature;

	bool                           enable_tdc_limit_feature;

	bool                           enable_pkg_pwr_tracking_feature;

	bool                           disable_uvd_power_tune_feature;

	struct ellesmere_pt_defaults       *power_tune_defaults;

	struct SMU74_Discrete_PmFuses  power_tune_table;

	uint32_t                       dte_tj_offset;

	uint32_t                       fast_watermark_threshold;



	/* ---- Phase Shedding ---- */

	bool                           vddc_phase_shed_control;



	/* ---- DI/DT ---- */

	struct ellesmere_display_timing        display_timing;



	/* ---- Thermal Temperature Setting ---- */

	struct ellesmere_dpmlevel_enable_mask     dpm_level_enable_mask;

	uint32_t                                  need_update_smu7_dpm_table;

	uint32_t                                  sclk_dpm_key_disabled;

	uint32_t                                  mclk_dpm_key_disabled;

	uint32_t                                  pcie_dpm_key_disabled;

	uint32_t                                  min_engine_clocks;

	struct ellesmere_pcie_perf_range          pcie_gen_performance;

	struct ellesmere_pcie_perf_range          pcie_lane_performance;

	struct ellesmere_pcie_perf_range          pcie_gen_power_saving;

	struct ellesmere_pcie_perf_range          pcie_lane_power_saving;

	bool                                      use_pcie_performance_levels;

	bool                                      use_pcie_power_saving_levels;

	uint32_t                                  activity_target[SMU74_MAX_LEVELS_GRAPHICS];

	uint32_t                                  mclk_activity_target;

	uint32_t                                  mclk_dpm0_activity_target;

	uint32_t                                  low_sclk_interrupt_threshold;

	uint32_t                                  last_mclk_dpm_enable_mask;

	bool                                      uvd_enabled;



	/* ---- Power Gating States ---- */

	bool                           uvd_power_gated;

	bool                           vce_power_gated;

	bool                           samu_power_gated;

	bool                           need_long_memory_training;



	/* Application power optimization parameters */

	bool                               update_up_hyst;

	bool                               update_down_hyst;

	uint32_t                           down_hyst;

	uint32_t                           up_hyst;

	uint32_t disable_dpm_mask;

	bool apply_optimized_settings;

};



/* To convert to Q8.8 format for firmware */

#define ELLESMERE_Q88_FORMAT_CONVERSION_UNIT             256



enum Ellesmere_I2CLineID {

	Ellesmere_I2CLineID_DDC1 = 0x90,

	Ellesmere_I2CLineID_DDC2 = 0x91,

	Ellesmere_I2CLineID_DDC3 = 0x92,

	Ellesmere_I2CLineID_DDC4 = 0x93,

	Ellesmere_I2CLineID_DDC5 = 0x94,

	Ellesmere_I2CLineID_DDC6 = 0x95,

	Ellesmere_I2CLineID_SCLSDA = 0x96,

	Ellesmere_I2CLineID_DDCVGA = 0x97

};



#define ELLESMERE_I2C_DDC1DATA          0

#define ELLESMERE_I2C_DDC1CLK           1

#define ELLESMERE_I2C_DDC2DATA          2

#define ELLESMERE_I2C_DDC2CLK           3

#define ELLESMERE_I2C_DDC3DATA          4

#define ELLESMERE_I2C_DDC3CLK           5

#define ELLESMERE_I2C_SDA               40

#define ELLESMERE_I2C_SCL               41

#define ELLESMERE_I2C_DDC4DATA          65

#define ELLESMERE_I2C_DDC4CLK           66

#define ELLESMERE_I2C_DDC5DATA          0x48

#define ELLESMERE_I2C_DDC5CLK           0x49

#define ELLESMERE_I2C_DDC6DATA          0x4a

#define ELLESMERE_I2C_DDC6CLK           0x4b

#define ELLESMERE_I2C_DDCVGADATA        0x4c

#define ELLESMERE_I2C_DDCVGACLK         0x4d



#define ELLESMERE_UNUSED_GPIO_PIN       0x7F



int ellesemere_hwmgr_init(struct pp_hwmgr *hwmgr);



#endif

drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.c

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