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Commit a210b028 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: replace ad-hoc dual-link lvds checks



... with is_dual_link_lvds introduced in

commit b0354385
Author: Takashi Iwai <tiwai@suse.de>
Date:   Tue Mar 20 13:07:05 2012 +0100

    drm/i915: Check VBIOS value for determining LVDS dual channel mode, too

All these checks predate this commit and have simply been overlooked.
Since we don't support switching between single-link and dual-link
modes anyway, this different checks could at best only get in the way
of refactorings, and in the worst case cause inconsistencies.

v2: Update the comment, we now have a solid way to figure out whether
we need dual-link lvds or not (falling back to vbt values as a last
resort). We still don't know how to switch between dual-link and
single link so leave that part intact. I'm not sure though whether
switching between these two modes makes any sense - we always drive
the panel at its fixed mode (with a fixed bpc) anyway ...

Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent dafd226c
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+6 −9
Original line number Original line Diff line number Diff line
@@ -690,13 +690,11 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
	intel_clock_t clock;
	intel_clock_t clock;
	int err = target;
	int err = target;


	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
	    (I915_READ(LVDS)) != 0) {
		/*
		/*
		 * For LVDS, if the panel is on, just rely on its current
		 * For LVDS just rely on its current settings for dual-channel.
		 * settings for dual-channel.  We haven't figured out how to
		 * We haven't figured out how to reliably set up different
		 * reliably set up different single/dual channel state, if we
		 * single/dual channel state, if we even can.
		 * even can.
		 */
		 */
		if (is_dual_link_lvds(dev_priv, LVDS))
		if (is_dual_link_lvds(dev_priv, LVDS))
			clock.p2 = limit->p2.p2_fast;
			clock.p2 = limit->p2.p2_fast;
@@ -766,8 +764,7 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
			lvds_reg = PCH_LVDS;
			lvds_reg = PCH_LVDS;
		else
		else
			lvds_reg = LVDS;
			lvds_reg = LVDS;
		if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
		if (is_dual_link_lvds(dev_priv, lvds_reg))
		    LVDS_CLKB_POWER_UP)
			clock.p2 = limit->p2.p2_fast;
			clock.p2 = limit->p2.p2_fast;
		else
		else
			clock.p2 = limit->p2.p2_slow;
			clock.p2 = limit->p2.p2_slow;
@@ -5359,7 +5356,7 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
	if (is_lvds) {
	if (is_lvds) {
		if ((intel_panel_use_ssc(dev_priv) &&
		if ((intel_panel_use_ssc(dev_priv) &&
		     dev_priv->lvds_ssc_freq == 100) ||
		     dev_priv->lvds_ssc_freq == 100) ||
		    (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
		    is_dual_link_lvds(dev_priv, PCH_LVDS))
			factor = 25;
			factor = 25;
	} else if (is_sdvo && is_tv)
	} else if (is_sdvo && is_tv)
		factor = 20;
		factor = 20;