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Commit a1d0d98d authored by David Gibson's avatar David Gibson Committed by Benjamin Herrenschmidt
Browse files

powerpc: Add WSP platform 



Add a platform for the Wire Speed Processor, based on the PPC A2.

This includes code for the ICS & OPB interrupt controllers, as well
as a SCOM backend, and SCOM based cpu bringup.

Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
Signed-off-by: default avatarJack Miller <jack@codezen.org>
Signed-off-by: default avatarIan Munsie <imunsie@au1.ibm.com>
Signed-off-by: default avatarMichael Ellerman <michael@ellerman.id.au>
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
parent 82578e19

arch/powerpc/include/asm/wsp.h

0 → 100644
+14 −0
Original line number Diff line number Diff line 
/*

 *  Copyright 2011 Michael Ellerman, IBM Corp.

 *

 *  This program is free software; you can redistribute it and/or

 *  modify it under the terms of the GNU General Public License

 *  as published by the Free Software Foundation; either version

 *  2 of the License, or (at your option) any later version.

 */

#ifndef __ASM_POWERPC_WSP_H

#define __ASM_POWERPC_WSP_H



extern int wsp_get_chip_id(struct device_node *dn);



#endif /* __ASM_POWERPC_WSP_H */

arch/powerpc/kernel/exceptions-64e.S

+23 −0
Original line number Diff line number Diff line
@@ -864,6 +864,20 @@ have_hes: 
	 * that will have to be made dependent on whether we are running under

	 * a hypervisor I suppose.

	 */



	/* BEWARE, MAGIC

	 * This code is called as an ordinary function on the boot CPU. But to

	 * avoid duplication, this code is also used in SCOM bringup of

	 * secondary CPUs. We read the code between the initial_tlb_code_start

	 * and initial_tlb_code_end labels one instruction at a time and RAM it

	 * into the new core via SCOM. That doesn't process branches, so there

	 * must be none between those two labels. It also means if this code

	 * ever takes any parameters, the SCOM code must also be updated to

	 * provide them.

	 */

	.globl a2_tlbinit_code_start

a2_tlbinit_code_start:



	ori	r11,r3,MAS0_WQ_ALLWAYS

	oris	r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */

	mtspr	SPRN_MAS0,r11
@@ -880,6 +894,9 @@ have_hes: 
	/* Write the TLB entry */

	tlbwe



	.globl a2_tlbinit_after_linear_map

a2_tlbinit_after_linear_map:



	/* Now we branch the new virtual address mapped by this entry */

	LOAD_REG_IMMEDIATE(r3,1f)

	mtctr	r3
@@ -931,10 +948,16 @@ have_hes: 
	cmpw	r3,r9

	blt	2b



	.globl  a2_tlbinit_after_iprot_flush

a2_tlbinit_after_iprot_flush:



	PPC_TLBILX(0,0,0)

	sync

	isync



	.globl a2_tlbinit_code_end

a2_tlbinit_code_end:



	/* We translate LR and return */

	mflr	r3

	tovirt(r3,r3)

arch/powerpc/platforms/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ source "arch/powerpc/platforms/embedded6xx/Kconfig" 
source "arch/powerpc/platforms/44x/Kconfig"

source "arch/powerpc/platforms/40x/Kconfig"

source "arch/powerpc/platforms/amigaone/Kconfig"

source "arch/powerpc/platforms/wsp/Kconfig"



config KVM_GUEST

	bool "KVM Guest support"

arch/powerpc/platforms/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -22,3 +22,4 @@ obj-$(CONFIG_PPC_CELL) += cell/ 
obj-$(CONFIG_PPC_PS3)		+= ps3/

obj-$(CONFIG_EMBEDDED6xx)	+= embedded6xx/

obj-$(CONFIG_AMIGAONE)		+= amigaone/

obj-$(CONFIG_PPC_WSP)		+= wsp/

arch/powerpc/platforms/wsp/Kconfig

0 → 100644
+28 −0
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config PPC_WSP

	bool

	default n



menu "WSP platform selection"

	depends on PPC_BOOK3E_64



config PPC_PSR2

	bool "PSR-2 platform"

	select PPC_A2

	select GENERIC_TBSYNC

	select PPC_SCOM

	select EPAPR_BOOT

	select PPC_WSP

	select PPC_XICS

	select PPC_ICP_NATIVE

	default y



endmenu



config PPC_A2_DD2

	bool "Support for DD2 based A2/WSP systems"

	depends on PPC_A2



config WORKAROUND_ERRATUM_463

	depends on PPC_A2_DD2

	bool "Workaround erratum 463"

	default y