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Commit a14a26ac authored by Ben Dooks's avatar Ben Dooks Committed by Russell King
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[ARM] 4515/1: S3C: Move uncompress code to plat-s3c 



Move the uncompress.h to plat-s3c

Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 3ec20520

include/asm-arm/arch-s3c2410/uncompress.h

+11 −131
Original line number Diff line number Diff line
@@ -13,153 +13,33 @@ 
#ifndef __ASM_ARCH_UNCOMPRESS_H

#define __ASM_ARCH_UNCOMPRESS_H



typedef unsigned int upf_t;	/* cannot include linux/serial_core.h */



/* defines for UART registers */

#include "asm/plat-s3c/regs-serial.h"

#include "asm/arch/regs-gpio.h"

#include "asm/plat-s3c/regs-watchdog.h"



#include <asm/arch/regs-gpio.h>

#include <asm/arch/map.h>



/* working in physical space... */

#undef S3C2410_GPIOREG

#undef S3C2410_WDOGREG



#define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x)))

#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))



#include <asm/plat-s3c/uncompress.h>



/* how many bytes we allow into the FIFO at a time in FIFO mode */

#define FIFO_MAX	 (14)



#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C_LOWLEVEL_UART_PORT)



static __inline__ void

uart_wr(unsigned int reg, unsigned int val)

{

	volatile unsigned int *ptr;



	ptr = (volatile unsigned int *)(reg + uart_base);

	*ptr = val;

}



static __inline__ unsigned int

uart_rd(unsigned int reg)

{

	volatile unsigned int *ptr;



	ptr = (volatile unsigned int *)(reg + uart_base);

	return *ptr;

}





/* we can deal with the case the UARTs are being run

 * in FIFO mode, so that we don't hold up our execution

 * waiting for tx to happen...

*/



static void putc(int ch)

static void arch_detect_cpu(void)

{

	int cpuid = S3C2410_GSTATUS1_2410;

	unsigned int cpuid;



#ifndef CONFIG_CPU_S3C2400

	cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1);

	cpuid &= S3C2410_GSTATUS1_IDMASK;

#endif



	if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {

		int level;



		while (1) {

			level = uart_rd(S3C2410_UFSTAT);



	if (cpuid == S3C2410_GSTATUS1_2440 ||

	    cpuid == S3C2410_GSTATUS1_2442) {

				level &= S3C2440_UFSTAT_TXMASK;

				level >>= S3C2440_UFSTAT_TXSHIFT;

			} else {

				level &= S3C2410_UFSTAT_TXMASK;

				level >>= S3C2410_UFSTAT_TXSHIFT;

			}



			if (level < FIFO_MAX)

				break;

		}



		fifo_mask = S3C2440_UFSTAT_TXMASK;

		fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;

	} else {

		/* not using fifos */



		while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)

			barrier();

		fifo_mask = S3C2410_UFSTAT_TXMASK;

		fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT;

	}



	/* write byte to transmission register */

	uart_wr(S3C2410_UTXH, ch);

}



static inline void flush(void)

{

}



#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)



/* CONFIG_S3C2410_BOOT_WATCHDOG

 *

 * Simple boot-time watchdog setup, to reboot the system if there is

 * any problem with the boot process

*/



#ifdef CONFIG_S3C2410_BOOT_WATCHDOG



#define WDOG_COUNT (0xff00)



static inline void arch_decomp_wdog(void)

{

	__raw_writel(WDOG_COUNT, S3C2410_WTCNT);

}



static void arch_decomp_wdog_start(void)

{

	__raw_writel(WDOG_COUNT, S3C2410_WTDAT);

	__raw_writel(WDOG_COUNT, S3C2410_WTCNT);

	__raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);

}



#else

#define arch_decomp_wdog_start()

#define arch_decomp_wdog()

#endif



#ifdef CONFIG_S3C2410_BOOT_ERROR_RESET



static void arch_decomp_error(const char *x)

{

	putstr("\n\n");

	putstr(x);

	putstr("\n\n -- System resetting\n");



	__raw_writel(0x4000, S3C2410_WTDAT);

	__raw_writel(0x4000, S3C2410_WTCNT);

	__raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);



	while(1);

}



#define arch_error arch_decomp_error

#endif



static void error(char *err);



static void

arch_decomp_setup(void)

{

	/* we may need to setup the uart(s) here if we are not running

	 * on an BAST... the BAST will have left the uarts configured

	 * after calling linux.

	 */



	arch_decomp_wdog_start();

}





#endif /* __ASM_ARCH_UNCOMPRESS_H */

include/asm-arm/plat-s3c/uncompress.h

0 → 100644
+155 −0
Original line number Diff line number Diff line 
/* linux/include/asm-arm/plat-s3c/uncompress.h

 *

 * Copyright 2003, 2007 Simtec Electronics

 *	http://armlinux.simtec.co.uk/

 *	Ben Dooks <ben@simtec.co.uk>

 *

 * S3C - uncompress code

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

*/



#ifndef __ASM_PLAT_UNCOMPRESS_H

#define __ASM_PLAT_UNCOMPRESS_H



typedef unsigned int upf_t;	/* cannot include linux/serial_core.h */



/* uart setup */



static unsigned int fifo_mask;

static unsigned int fifo_max;



/* forward declerations */



static void arch_detect_cpu(void);



/* defines for UART registers */



#include "asm/plat-s3c/regs-serial.h"

#include "asm/plat-s3c/regs-watchdog.h"



/* working in physical space... */

#undef S3C2410_WDOGREG

#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))



/* how many bytes we allow into the FIFO at a time in FIFO mode */

#define FIFO_MAX	 (14)



#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C_LOWLEVEL_UART_PORT)



static __inline__ void

uart_wr(unsigned int reg, unsigned int val)

{

	volatile unsigned int *ptr;



	ptr = (volatile unsigned int *)(reg + uart_base);

	*ptr = val;

}



static __inline__ unsigned int

uart_rd(unsigned int reg)

{

	volatile unsigned int *ptr;



	ptr = (volatile unsigned int *)(reg + uart_base);

	return *ptr;

}



/* we can deal with the case the UARTs are being run

 * in FIFO mode, so that we don't hold up our execution

 * waiting for tx to happen...

*/



static void putc(int ch)

{

	if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {

		int level;



		while (1) {

			level = uart_rd(S3C2410_UFSTAT);

			level &= fifo_mask;



			if (level < fifo_max)

				break;

		}



	} else {

		/* not using fifos */



		while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)

			barrier();

	}



	/* write byte to transmission register */

	uart_wr(S3C2410_UTXH, ch);

}



static inline void flush(void)

{

}



#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)



/* CONFIG_S3C2410_BOOT_WATCHDOG

 *

 * Simple boot-time watchdog setup, to reboot the system if there is

 * any problem with the boot process

*/



#ifdef CONFIG_S3C2410_BOOT_WATCHDOG



#define WDOG_COUNT (0xff00)



static inline void arch_decomp_wdog(void)

{

	__raw_writel(WDOG_COUNT, S3C2410_WTCNT);

}



static void arch_decomp_wdog_start(void)

{

	__raw_writel(WDOG_COUNT, S3C2410_WTDAT);

	__raw_writel(WDOG_COUNT, S3C2410_WTCNT);

	__raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);

}



#else

#define arch_decomp_wdog_start()

#define arch_decomp_wdog()

#endif



#ifdef CONFIG_S3C2410_BOOT_ERROR_RESET



static void arch_decomp_error(const char *x)

{

	putstr("\n\n");

	putstr(x);

	putstr("\n\n -- System resetting\n");



	__raw_writel(0x4000, S3C2410_WTDAT);

	__raw_writel(0x4000, S3C2410_WTCNT);

	__raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);



	while(1);

}



#define arch_error arch_decomp_error

#endif



static void error(char *err);



static void

arch_decomp_setup(void)

{

	/* we may need to setup the uart(s) here if we are not running

	 * on an BAST... the BAST will have left the uarts configured

	 * after calling linux.

	 */



	arch_detect_cpu();

	arch_decomp_wdog_start();

}





#endif /* __ASM_PLAT_UNCOMPRESS_H */