Loading drivers/scsi/ahci.c +8 −12 Original line number Diff line number Diff line Loading @@ -50,6 +50,7 @@ enum { AHCI_CMD_SLOT_SZ = 32 * 32, AHCI_RX_FIS_SZ = 256, AHCI_CMD_TBL_HDR = 0x80, AHCI_CMD_TBL_CDB = 0x40, AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16), AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ + AHCI_RX_FIS_SZ, Loading Loading @@ -510,7 +511,8 @@ static void ahci_fill_sg(struct ata_queued_cmd *qc) static void ahci_qc_prep(struct ata_queued_cmd *qc) { struct ahci_port_priv *pp = qc->ap->private_data; struct ata_port *ap = qc->ap; struct ahci_port_priv *pp = ap->private_data; u32 opts; const u32 cmd_fis_len = 5; /* five dwords */ Loading @@ -522,18 +524,8 @@ static void ahci_qc_prep(struct ata_queued_cmd *qc) opts = (qc->n_elem << 16) | cmd_fis_len; if (qc->tf.flags & ATA_TFLAG_WRITE) opts |= AHCI_CMD_WRITE; switch (qc->tf.protocol) { case ATA_PROT_ATAPI: case ATA_PROT_ATAPI_NODATA: case ATA_PROT_ATAPI_DMA: if (is_atapi_taskfile(&qc->tf)) opts |= AHCI_CMD_ATAPI; break; default: /* do nothing */ break; } pp->cmd_slot[0].opts = cpu_to_le32(opts); pp->cmd_slot[0].status = 0; Loading @@ -545,6 +537,10 @@ static void ahci_qc_prep(struct ata_queued_cmd *qc) * a SATA Register - Host to Device command FIS. */ ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0); if (opts & AHCI_CMD_ATAPI) { memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, ap->cdb_len); } if (!(qc->flags & ATA_QCFLAG_DMAMAP)) return; Loading Loading
drivers/scsi/ahci.c +8 −12 Original line number Diff line number Diff line Loading @@ -50,6 +50,7 @@ enum { AHCI_CMD_SLOT_SZ = 32 * 32, AHCI_RX_FIS_SZ = 256, AHCI_CMD_TBL_HDR = 0x80, AHCI_CMD_TBL_CDB = 0x40, AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16), AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ + AHCI_RX_FIS_SZ, Loading Loading @@ -510,7 +511,8 @@ static void ahci_fill_sg(struct ata_queued_cmd *qc) static void ahci_qc_prep(struct ata_queued_cmd *qc) { struct ahci_port_priv *pp = qc->ap->private_data; struct ata_port *ap = qc->ap; struct ahci_port_priv *pp = ap->private_data; u32 opts; const u32 cmd_fis_len = 5; /* five dwords */ Loading @@ -522,18 +524,8 @@ static void ahci_qc_prep(struct ata_queued_cmd *qc) opts = (qc->n_elem << 16) | cmd_fis_len; if (qc->tf.flags & ATA_TFLAG_WRITE) opts |= AHCI_CMD_WRITE; switch (qc->tf.protocol) { case ATA_PROT_ATAPI: case ATA_PROT_ATAPI_NODATA: case ATA_PROT_ATAPI_DMA: if (is_atapi_taskfile(&qc->tf)) opts |= AHCI_CMD_ATAPI; break; default: /* do nothing */ break; } pp->cmd_slot[0].opts = cpu_to_le32(opts); pp->cmd_slot[0].status = 0; Loading @@ -545,6 +537,10 @@ static void ahci_qc_prep(struct ata_queued_cmd *qc) * a SATA Register - Host to Device command FIS. */ ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0); if (opts & AHCI_CMD_ATAPI) { memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, ap->cdb_len); } if (!(qc->flags & ATA_QCFLAG_DMAMAP)) return; Loading