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Commit a0c85e96 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/staging 

* 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/staging:
  hwmon: (lm85) extend to support EMC6D103 chips
  MAINTAINERS: Remove stale hwmon quilt tree
  hwmon: (k10temp) add support for AMD Family 12h/14h CPUs
  hwmon: (jc42) do not allow writing to locked registers
  hwmon: (jc42) more helpful documentation
  hwmon: (jc42) fix type mismatch
parents e5871372 f065a93e

Documentation/hwmon/jc42

+15 −6
Original line number Diff line number Diff line
@@ -51,7 +51,8 @@ Supported chips: 
  * JEDEC JC 42.4 compliant temperature sensor chips

    Prefix: 'jc42'

    Addresses scanned: I2C 0x18 - 0x1f

    Datasheet: -

    Datasheet:

	http://www.jedec.org/sites/default/files/docs/4_01_04R19.pdf



Author:

	Guenter Roeck <guenter.roeck@ericsson.com>
@@ -60,7 +61,11 @@ Author: 
Description

-----------



This driver implements support for JEDEC JC 42.4 compliant temperature sensors.

This driver implements support for JEDEC JC 42.4 compliant temperature sensors,

which are used on many DDR3 memory modules for mobile devices and servers. Some

systems use the sensor to prevent memory overheating by automatically throttling

the memory controller.



The driver auto-detects the chips listed above, but can be manually instantiated

to support other JC 42.4 compliant chips.
@@ -81,15 +86,19 @@ limits. The chip supports only a single register to configure the hysteresis, 
which applies to all limits. This register can be written by writing into

temp1_crit_hyst. Other hysteresis attributes are read-only.



If the BIOS has configured the sensor for automatic temperature management, it

is likely that it has locked the registers, i.e., that the temperature limits

cannot be changed.



Sysfs entries

-------------



temp1_input		Temperature (RO)

temp1_min		Minimum temperature (RW)

temp1_max		Maximum temperature (RW)

temp1_crit		Critical high temperature (RW)

temp1_min		Minimum temperature (RO or RW)

temp1_max		Maximum temperature (RO or RW)

temp1_crit		Critical high temperature (RO or RW)



temp1_crit_hyst		Critical hysteresis temperature (RW)

temp1_crit_hyst		Critical hysteresis temperature (RO or RW)

temp1_max_hyst		Maximum hysteresis temperature (RO)



temp1_min_alarm		Temperature low alarm

Documentation/hwmon/k10temp

+7 −1
Original line number Diff line number Diff line
@@ -9,6 +9,8 @@ Supported chips: 
  Socket S1G3: Athlon II, Sempron, Turion II

* AMD Family 11h processors:

  Socket S1G2: Athlon (X2), Sempron (X2), Turion X2 (Ultra)

* AMD Family 12h processors: "Llano"

* AMD Family 14h processors: "Brazos" (C/E/G-Series)



  Prefix: 'k10temp'

  Addresses scanned: PCI space
@@ -17,10 +19,14 @@ Supported chips: 
    http://support.amd.com/us/Processor_TechDocs/31116.pdf

  BIOS and Kernel Developer's Guide (BKDG) for AMD Family 11h Processors:

    http://support.amd.com/us/Processor_TechDocs/41256.pdf

  BIOS and Kernel Developer's Guide (BKDG) for AMD Family 14h Models 00h-0Fh Processors:

    http://support.amd.com/us/Processor_TechDocs/43170.pdf

  Revision Guide for AMD Family 10h Processors:

    http://support.amd.com/us/Processor_TechDocs/41322.pdf

  Revision Guide for AMD Family 11h Processors:

    http://support.amd.com/us/Processor_TechDocs/41788.pdf

  Revision Guide for AMD Family 14h Models 00h-0Fh Processors:

    http://support.amd.com/us/Processor_TechDocs/47534.pdf

  AMD Family 11h Processor Power and Thermal Data Sheet for Notebooks:

    http://support.amd.com/us/Processor_TechDocs/43373.pdf

  AMD Family 10h Server and Workstation Processor Power and Thermal Data Sheet:
@@ -34,7 +40,7 @@ Description 
-----------



This driver permits reading of the internal temperature sensor of AMD

Family 10h and 11h processors.

Family 10h/11h/12h/14h processors.



All these processors have a sensor, but on those for Socket F or AM2+,

the sensor may return inconsistent values (erratum 319).  The driver

MAINTAINERS

+0 −1
Original line number Diff line number Diff line
@@ -2873,7 +2873,6 @@ M: Guenter Roeck <guenter.roeck@ericsson.com> 
L:	lm-sensors@lm-sensors.org

W:	http://www.lm-sensors.org/

T:	quilt kernel.org/pub/linux/kernel/people/jdelvare/linux-2.6/jdelvare-hwmon/

T:	quilt kernel.org/pub/linux/kernel/people/groeck/linux-staging/

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git

S:	Maintained

F:	Documentation/hwmon/

drivers/hwmon/Kconfig

+10 −9
Original line number Diff line number Diff line
@@ -238,13 +238,13 @@ config SENSORS_K8TEMP 
	  will be called k8temp.



config SENSORS_K10TEMP

	tristate "AMD Phenom/Sempron/Turion/Opteron temperature sensor"

	tristate "AMD Family 10h/11h/12h/14h temperature sensor"

	depends on X86 && PCI

	help

	  If you say yes here you get support for the temperature

	  sensor(s) inside your CPU. Supported are later revisions of

	  the AMD Family 10h and all revisions of the AMD Family 11h

	  microarchitectures.

	  the AMD Family 10h and all revisions of the AMD Family 11h,

	  12h (Llano), and 14h (Brazos) microarchitectures.



	  This driver can also be built as a module.  If so, the module

	  will be called k10temp.
@@ -455,13 +455,14 @@ config SENSORS_JZ4740 
	  called jz4740-hwmon.



config SENSORS_JC42

	tristate "JEDEC JC42.4 compliant temperature sensors"

	tristate "JEDEC JC42.4 compliant memory module temperature sensors"

	depends on I2C

	help

	  If you say yes here you get support for Jedec JC42.4 compliant

	  temperature sensors. Support will include, but not be limited to,

	  ADT7408, CAT34TS02,, CAT6095, MAX6604, MCP9805, MCP98242, MCP98243,

	  MCP9843, SE97, SE98, STTS424, TSE2002B3, and TS3000B3.

	  If you say yes here, you get support for JEDEC JC42.4 compliant

	  temperature sensors, which are used on many DDR3 memory modules for

	  mobile devices and servers.  Support will include, but not be limited

	  to, ADT7408, CAT34TS02, CAT6095, MAX6604, MCP9805, MCP98242, MCP98243,

	  MCP9843, SE97, SE98, STTS424(E), TSE2002B3, and TS3000B3.



	  This driver can also be built as a module.  If so, the module

	  will be called jc42.
@@ -574,7 +575,7 @@ config SENSORS_LM85 
	help

	  If you say yes here you get support for National Semiconductor LM85

	  sensor chips and clones: ADM1027, ADT7463, ADT7468, EMC6D100,

	  EMC6D101 and EMC6D102.

	  EMC6D101, EMC6D102, and EMC6D103.



	  This driver can also be built as a module.  If so, the module

	  will be called lm85.

drivers/hwmon/jc42.c

+30 −5
Original line number Diff line number Diff line
@@ -53,6 +53,8 @@ static const unsigned short normal_i2c[] = { 


/* Configuration register defines */

#define JC42_CFG_CRIT_ONLY	(1 << 2)

#define JC42_CFG_TCRIT_LOCK	(1 << 6)

#define JC42_CFG_EVENT_LOCK	(1 << 7)

#define JC42_CFG_SHUTDOWN	(1 << 8)

#define JC42_CFG_HYST_SHIFT	9

#define JC42_CFG_HYST_MASK	0x03
@@ -332,7 +334,7 @@ static ssize_t set_temp_crit_hyst(struct device *dev, 
{

	struct i2c_client *client = to_i2c_client(dev);

	struct jc42_data *data = i2c_get_clientdata(client);

	long val;

	unsigned long val;

	int diff, hyst;

	int err;

	int ret = count;
@@ -380,14 +382,14 @@ static ssize_t show_alarm(struct device *dev, 


static DEVICE_ATTR(temp1_input, S_IRUGO,

		   show_temp_input, NULL);

static DEVICE_ATTR(temp1_crit, S_IWUSR | S_IRUGO,

static DEVICE_ATTR(temp1_crit, S_IRUGO,

		   show_temp_crit, set_temp_crit);

static DEVICE_ATTR(temp1_min, S_IWUSR | S_IRUGO,

static DEVICE_ATTR(temp1_min, S_IRUGO,

		   show_temp_min, set_temp_min);

static DEVICE_ATTR(temp1_max, S_IWUSR | S_IRUGO,

static DEVICE_ATTR(temp1_max, S_IRUGO,

		   show_temp_max, set_temp_max);



static DEVICE_ATTR(temp1_crit_hyst, S_IWUSR | S_IRUGO,

static DEVICE_ATTR(temp1_crit_hyst, S_IRUGO,

		   show_temp_crit_hyst, set_temp_crit_hyst);

static DEVICE_ATTR(temp1_max_hyst, S_IRUGO,

		   show_temp_max_hyst, NULL);
@@ -412,8 +414,31 @@ static struct attribute *jc42_attributes[] = { 
	NULL

};



static mode_t jc42_attribute_mode(struct kobject *kobj,

				  struct attribute *attr, int index)

{

	struct device *dev = container_of(kobj, struct device, kobj);

	struct i2c_client *client = to_i2c_client(dev);

	struct jc42_data *data = i2c_get_clientdata(client);

	unsigned int config = data->config;

	bool readonly;



	if (attr == &dev_attr_temp1_crit.attr)

		readonly = config & JC42_CFG_TCRIT_LOCK;

	else if (attr == &dev_attr_temp1_min.attr ||

		 attr == &dev_attr_temp1_max.attr)

		readonly = config & JC42_CFG_EVENT_LOCK;

	else if (attr == &dev_attr_temp1_crit_hyst.attr)

		readonly = config & (JC42_CFG_EVENT_LOCK | JC42_CFG_TCRIT_LOCK);

	else

		readonly = true;



	return S_IRUGO | (readonly ? 0 : S_IWUSR);

}



static const struct attribute_group jc42_group = {

	.attrs = jc42_attributes,

	.is_visible = jc42_attribute_mode,

};



/* Return 0 if detection is successful, -ENODEV otherwise */