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Commit 9f1ac560 authored by Thierry Reding's avatar Thierry Reding Committed by Stephen Warren
Browse files

ARM: tegra: Add SPI controller nodes for Tegra124 



The SPI controllers on Tegra124 are compatible with those found on the
Tegra114 SoC.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent f5cb19b4

arch/arm/boot/dts/tegra124.dtsi

+90 −0
Original line number Diff line number Diff line
@@ -277,6 +277,96 @@ 
		status = "disabled";

	};



	spi@7000d400 {

		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";

		reg = <0x7000d400 0x200>;

		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		clocks = <&tegra_car TEGRA124_CLK_SBC1>;

		clock-names = "spi";

		resets = <&tegra_car 41>;

		reset-names = "spi";

		dmas = <&apbdma 15>, <&apbdma 15>;

		dma-names = "rx", "tx";

		status = "disabled";

	};



	spi@7000d600 {

		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";

		reg = <0x7000d600 0x200>;

		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		clocks = <&tegra_car TEGRA124_CLK_SBC2>;

		clock-names = "spi";

		resets = <&tegra_car 44>;

		reset-names = "spi";

		dmas = <&apbdma 16>, <&apbdma 16>;

		dma-names = "rx", "tx";

		status = "disabled";

	};



	spi@7000d800 {

		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";

		reg = <0x7000d800 0x200>;

		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		clocks = <&tegra_car TEGRA124_CLK_SBC3>;

		clock-names = "spi";

		resets = <&tegra_car 46>;

		reset-names = "spi";

		dmas = <&apbdma 17>, <&apbdma 17>;

		dma-names = "rx", "tx";

		status = "disabled";

	};



	spi@7000da00 {

		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";

		reg = <0x7000da00 0x200>;

		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		clocks = <&tegra_car TEGRA124_CLK_SBC4>;

		clock-names = "spi";

		resets = <&tegra_car 68>;

		reset-names = "spi";

		dmas = <&apbdma 18>, <&apbdma 18>;

		dma-names = "rx", "tx";

		status = "disabled";

	};



	spi@7000dc00 {

		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";

		reg = <0x7000dc00 0x200>;

		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		clocks = <&tegra_car TEGRA124_CLK_SBC5>;

		clock-names = "spi";

		resets = <&tegra_car 104>;

		reset-names = "spi";

		dmas = <&apbdma 27>, <&apbdma 27>;

		dma-names = "rx", "tx";

		status = "disabled";

	};



	spi@7000de00 {

		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";

		reg = <0x7000de00 0x200>;

		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		clocks = <&tegra_car TEGRA124_CLK_SBC6>;

		clock-names = "spi";

		resets = <&tegra_car 105>;

		reset-names = "spi";

		dmas = <&apbdma 28>, <&apbdma 28>;

		dma-names = "rx", "tx";

		status = "disabled";

	};



	rtc@7000e000 {

		compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";

		reg = <0x7000e000 0x100>;