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Commit 9f05027c authored by Will Deacon's avatar Will Deacon Committed by Russell King
Browse files

ARM: 6388/1: errata: DMB operation may be faulty 



On versions of the Cortex-A9 up to and including r2p2, under rare
circumstances, a DMB instruction between 2 write operations may not
ensure the correct visibility ordering of the 2 writes.

This workaround sets a bit in the diagnostic register of the Cortex-A9,
causing the DMB instruction to behave like a DSB, which functions
correctly on the affected cores.

Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 6491848d

arch/arm/Kconfig

+12 −0
Original line number Diff line number Diff line
@@ -1051,6 +1051,18 @@ config ARM_ERRATA_460075 
	  ACTLR register. Note that setting specific bits in the ACTLR register

	  may not be available in non-secure mode.



config ARM_ERRATA_742230

	bool "ARM errata: DMB operation may be faulty"

	depends on CPU_V7 && SMP

	help

	  This option enables the workaround for the 742230 Cortex-A9

	  (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction

	  between two write operations may not ensure the correct visibility

	  ordering of the two writes. This workaround sets a specific bit in

	  the diagnostic register of the Cortex-A9 which causes the DMB

	  instruction to behave as a DSB, ensuring the correct behaviour of

	  the two writes.



config PL310_ERRATA_588369

	bool "Clean & Invalidate maintenance operations do not invalidate clean lines"

	depends on CACHE_L2X0 && ARCH_OMAP4

arch/arm/mm/proc-v7.S

+14 −2
Original line number Diff line number Diff line
@@ -201,7 +201,7 @@ __v7_setup: 
	mrc	p15, 0, r0, c0, c0, 0		@ read main ID register

	and	r10, r0, #0xff000000		@ ARM?

	teq	r10, #0x41000000

	bne	2f

	bne	3f

	and	r5, r0, #0x00f00000		@ variant

	and	r6, r0, #0x0000000f		@ revision

	orr	r6, r6, r5, lsr #20-4		@ combine variant and revision
@@ -231,8 +231,20 @@ __v7_setup: 
	orreq	r10, r10, #(1 << 22)		@ set the Write Allocate disable bit

	mcreq	p15, 1, r10, c9, c0, 2		@ write the L2 cache aux ctrl register

#endif

	b	3f



	/* Cortex-A9 Errata */

2:	ldr	r10, =0x00000c09		@ Cortex-A9 primary part number

	teq	r0, r10

	bne	3f

#ifdef CONFIG_ARM_ERRATA_742230

	cmp	r6, #0x22			@ only present up to r2p2

	mrcle	p15, 0, r10, c15, c0, 1		@ read diagnostic register

	orrle	r10, r10, #1 << 4		@ set bit #4

	mcrle	p15, 0, r10, c15, c0, 1		@ write diagnostic register

#endif



2:	mov	r10, #0

3:	mov	r10, #0

#ifdef HARVARD_CACHE

	mcr	p15, 0, r10, c7, c5, 0		@ I+BTB cache invalidate

#endif