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Commit 9ef8537e authored by Christian König's avatar Christian König Committed by Alex Deucher
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drm/radeon: don't use fractional dividers on RS[78]80 if SS is enabled 



Seems to cause problems for some older hardware. Kudos to Thom Kouwenhoven
for working a lot with the PLLs and figuring this out.

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ccaa2c12

drivers/gpu/drm/radeon/atombios_crtc.c

+3 −2
Original line number Diff line number Diff line
@@ -589,7 +589,8 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, 
		if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))

			radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;

		/* use frac fb div on RS780/RS880 */

		if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))

		if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))

		    && !radeon_crtc->ss_enabled)

			radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;

		if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)

			radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
@@ -626,7 +627,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, 
			if (radeon_crtc->ss.refdiv) {

				radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;

				radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;

				if (ASIC_IS_AVIVO(rdev))

				if (rdev->family >= CHIP_RV770)

					radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;

			}

		}