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Commit 9ec0db71 authored by Giuseppe CAVALLARO's avatar Giuseppe CAVALLARO Committed by David S. Miller
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net: icplus: fix interrupt mask 



This patch fixes the interrupt mask for IC101 A/G devices
and now enables the link/speed/duplex interrupts.
This is done by setting the "INTR pin used" bit and cleaning
all the other bits in the Register 17.

Reported-by: default avatarStuart Menefy <stuart.menefy@st.com>
Signed-off-by: default avatarGiuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 3ab2cdd0

drivers/net/phy/icplus.c

+7 −0
Original line number Diff line number Diff line
@@ -41,6 +41,8 @@ MODULE_LICENSE("GPL"); 
#define IP1001_APS_ON			11	/* IP1001 APS Mode  bit */

#define IP101A_G_APS_ON			2	/* IP101A/G APS Mode bit */

#define IP101A_G_IRQ_CONF_STATUS	0x11	/* Conf Info IRQ & Status Reg */

#define	IP101A_G_IRQ_PIN_USED		(1<<15) /* INTR pin used */

#define	IP101A_G_IRQ_DEFAULT		IP101A_G_IRQ_PIN_USED



static int ip175c_config_init(struct phy_device *phydev)

{
@@ -136,6 +138,11 @@ static int ip1001_config_init(struct phy_device *phydev) 
	if (c < 0)

		return c;



	/* INTR pin used: speed/link/duplex will cause an interrupt */

	c = phy_write(phydev, IP101A_G_IRQ_CONF_STATUS, IP101A_G_IRQ_DEFAULT);

	if (c < 0)

		return c;



	if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {

		/* Additional delay (2ns) used to adjust RX clock phase

		 * at RGMII interface */