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Commit 9db52c78 authored by Shannon Zhao's avatar Shannon Zhao Committed by Marc Zyngier
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arm64: KVM: Add access handler for PMINTENSET and PMINTENCLR register 



Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a handler to emulate writing
PMINTENSET or PMINTENCLR register.

Signed-off-by: default avatarShannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: default avatarAndrew Jones <drjones@redhat.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent 9feb21ac

arch/arm64/include/asm/kvm_host.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -127,6 +127,7 @@ enum vcpu_sysreg { 
	PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,

	PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,

	PMCCFILTR_EL0,	/* Cycle Count Filter Register */

	PMCCFILTR_EL0,	/* Cycle Count Filter Register */

	PMCNTENSET_EL0,	/* Count Enable Set Register */

	PMCNTENSET_EL0,	/* Count Enable Set Register */

	PMINTENSET_EL1,	/* Interrupt Enable Set Register */





	/* 32bit specific registers. Keep them at the end of the range */

	/* 32bit specific registers. Keep them at the end of the range */

	DACR32_EL2,	/* Domain Access Control Register */

	DACR32_EL2,	/* Domain Access Control Register */

arch/arm64/kvm/sys_regs.c

+28 −4
Original line number Original line Diff line number Diff line
@@ -626,6 +626,30 @@ static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 
	return true;

	return true;

}

}





static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,

			   const struct sys_reg_desc *r)

{

	u64 mask = kvm_pmu_valid_counter_mask(vcpu);



	if (!kvm_arm_pmu_v3_ready(vcpu))

		return trap_raz_wi(vcpu, p, r);



	if (p->is_write) {

		u64 val = p->regval & mask;



		if (r->Op2 & 0x1)

			/* accessing PMINTENSET_EL1 */

			vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;

		else

			/* accessing PMINTENCLR_EL1 */

			vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;

	} else {

		p->regval = vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;

	}



	return true;

}



/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */

/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */

#define DBG_BCR_BVR_WCR_WVR_EL1(n)					\

#define DBG_BCR_BVR_WCR_WVR_EL1(n)					\

	/* DBGBVRn_EL1 */						\

	/* DBGBVRn_EL1 */						\
@@ -784,10 +808,10 @@ static const struct sys_reg_desc sys_reg_descs[] = { 




	/* PMINTENSET_EL1 */

	/* PMINTENSET_EL1 */

	{ Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),

	{ Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),

	  trap_raz_wi },

	  access_pminten, reset_unknown, PMINTENSET_EL1 },

	/* PMINTENCLR_EL1 */

	/* PMINTENCLR_EL1 */

	{ Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),

	{ Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),

	  trap_raz_wi },

	  access_pminten, NULL, PMINTENSET_EL1 },





	/* MAIR_EL1 */

	/* MAIR_EL1 */

	{ Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),

	{ Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
@@ -1182,8 +1206,8 @@ static const struct sys_reg_desc cp15_regs[] = { 
	{ Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },

	{ Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },

	{ Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },

	{ Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },

	{ Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },

	{ Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },

	{ Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi },

	{ Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },

	{ Op1( 0), CRn( 9), CRm(14), Op2( 2), trap_raz_wi },

	{ Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },





	{ Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },

	{ Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },

	{ Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },

	{ Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },