Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 9c5a3d72 authored by Ralf Baechle's avatar Ralf Baechle
Browse files

[MIPS] Handle aliases in vmalloc correctly. 



flush_cache_vmap / flush_cache_vunmap were calling flush_cache_all which -
having been deprecated - turned into a nop ...

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 950b0d28

arch/mips/mm/c-r4k.c

+14 −0
Original line number Diff line number Diff line
@@ -361,6 +361,16 @@ static inline int has_valid_asid(const struct mm_struct *mm) 
#endif

}



static void r4k__flush_cache_vmap(void)

{

	r4k_blast_dcache();

}



static void r4k__flush_cache_vunmap(void)

{

	r4k_blast_dcache();

}



static inline void local_r4k_flush_cache_range(void * args)

{

	struct vm_area_struct *vma = args;
@@ -1281,6 +1291,10 @@ void __cpuinit r4k_cache_init(void) 
					PAGE_SIZE - 1);

	else

		shm_align_mask = PAGE_SIZE-1;



	__flush_cache_vmap	= r4k__flush_cache_vmap;

	__flush_cache_vunmap	= r4k__flush_cache_vunmap;



	flush_cache_all		= cache_noop;

	__flush_cache_all	= r4k___flush_cache_all;

	flush_cache_mm		= r4k_flush_cache_mm;

arch/mips/mm/c-tx39.c

+15 −0
Original line number Diff line number Diff line
@@ -122,6 +122,16 @@ static inline void tx39_blast_icache(void) 
	local_irq_restore(flags);

}



static void tx39__flush_cache_vmap(void)

{

	tx39_blast_dcache();

}



static void tx39__flush_cache_vunmap(void)

{

	tx39_blast_dcache();

}



static inline void tx39_flush_cache_all(void)

{

	if (!cpu_has_dc_aliases)
@@ -344,6 +354,8 @@ void __cpuinit tx39_cache_init(void) 
	switch (current_cpu_type()) {

	case CPU_TX3912:

		/* TX39/H core (writethru direct-map cache) */

		__flush_cache_vmap	= tx39__flush_cache_vmap;

		__flush_cache_vunmap	= tx39__flush_cache_vunmap;

		flush_cache_all	= tx39h_flush_icache_all;

		__flush_cache_all	= tx39h_flush_icache_all;

		flush_cache_mm		= (void *) tx39h_flush_icache_all;
@@ -369,6 +381,9 @@ void __cpuinit tx39_cache_init(void) 
		write_c0_wired(0);	/* set 8 on reset... */

		/* board-dependent init code may set WBON */



		__flush_cache_vmap	= tx39__flush_cache_vmap;

		__flush_cache_vunmap	= tx39__flush_cache_vunmap;



		flush_cache_all = tx39_flush_cache_all;

		__flush_cache_all = tx39___flush_cache_all;

		flush_cache_mm = tx39_flush_cache_mm;

arch/mips/mm/cache.c

+3 −0
Original line number Diff line number Diff line
@@ -30,6 +30,9 @@ void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, 
	unsigned long pfn);

void (*flush_icache_range)(unsigned long start, unsigned long end);



void (*__flush_cache_vmap)(void);

void (*__flush_cache_vunmap)(void);



/* MIPS specific cache operations */

void (*flush_cache_sigtramp)(unsigned long addr);

void (*local_flush_data_cache_page)(void * addr);

include/asm-mips/cacheflush.h

+16 −2
Original line number Diff line number Diff line
@@ -63,8 +63,22 @@ static inline void flush_icache_page(struct vm_area_struct *vma, 
}



extern void (*flush_icache_range)(unsigned long start, unsigned long end);

#define flush_cache_vmap(start, end)		flush_cache_all()

#define flush_cache_vunmap(start, end)		flush_cache_all()



extern void (*__flush_cache_vmap)(void);



static inline void flush_cache_vmap(unsigned long start, unsigned long end)

{

	if (cpu_has_dc_aliases)

		__flush_cache_vmap();

}



extern void (*__flush_cache_vunmap)(void);



static inline void flush_cache_vunmap(unsigned long start, unsigned long end)

{

	if (cpu_has_dc_aliases)

		__flush_cache_vunmap();

}



extern void copy_to_user_page(struct vm_area_struct *vma,

	struct page *page, unsigned long vaddr, void *dst, const void *src,