ASoC: fsl_spdif: Add indentation for binding doc to increase readability

  - clocks		: Contains an entry for each entry in clock-names.

  - clock-names		: Includes the following entries:

	"core"		The core clock of spdif controller

	"core"		  The core clock of spdif controller.

	"rxtx<0-7>"	  Clock source list for tx and rx clock.

			This clock list should be identical to

			the source list connecting to the spdif

			clock mux in "SPDIF Transceiver Clock

			Diagram" of SoC reference manual. It

			can also be referred to TxClk_Source

			bit of register SPDIF_STC.

   - big-endian : If this property is absent, the native endian mode will

   be in use as default, or the big endian mode will be in use for all the

   device registers.

			  This clock list should be identical to the source

			  list connecting to the spdif clock mux in "SPDIF

			  Transceiver Clock Diagram" of SoC reference manual.

			  It can also be referred to TxClk_Source bit of

			  register SPDIF_STC.

   - big-endian		: If this property is absent, the native endian mode

			  will be in use as default, or the big endian mode

			  will be in use for all the device registers.

Example: