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Commit 9b66bfb2 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-uv-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 UV debug changes from Ingo Molnar:
 "Various SGI UV debuggability improvements, amongst them KDB support,
  with related core KDB enabling patches changing kernel/debug/kdb/"

* 'x86-uv-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  Revert "x86/UV: Add uvtrace support"
  x86/UV: Add call to KGDB/KDB from NMI handler
  kdb: Add support for external NMI handler to call KGDB/KDB
  x86/UV: Check for alloc_cpumask_var() failures properly in uv_nmi_setup()
  x86/UV: Add uvtrace support
  x86/UV: Add kdump to UV NMI handler
  x86/UV: Add summary of cpu activity to UV NMI handler
  x86/UV: Update UV support for external NMI signals
  x86/UV: Move NMI support
parents c2136301 b5dfcb09

arch/x86/include/asm/uv/uv.h

+2 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ extern enum uv_system_type get_uv_system_type(void); 
extern int is_uv_system(void);

extern void uv_cpu_init(void);

extern void uv_nmi_init(void);

extern void uv_register_nmi_notifier(void);

extern void uv_system_init(void);

extern const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,

						 struct mm_struct *mm,
@@ -25,6 +26,7 @@ static inline enum uv_system_type get_uv_system_type(void) { return UV_NONE; } 
static inline int is_uv_system(void)	{ return 0; }

static inline void uv_cpu_init(void)	{ }

static inline void uv_system_init(void)	{ }

static inline void uv_register_nmi_notifier(void) { }

static inline const struct cpumask *

uv_flush_tlb_others(const struct cpumask *cpumask, struct mm_struct *mm,

		    unsigned long start, unsigned long end, unsigned int cpu)

arch/x86/include/asm/uv/uv_hub.h

+55 −2
Original line number Diff line number Diff line
@@ -502,8 +502,8 @@ struct uv_blade_info { 
	unsigned short	nr_online_cpus;

	unsigned short	pnode;

	short		memory_nid;

	spinlock_t	nmi_lock;

	unsigned long	nmi_count;

	spinlock_t	nmi_lock;	/* obsolete, see uv_hub_nmi */

	unsigned long	nmi_count;	/* obsolete, see uv_hub_nmi */

};

extern struct uv_blade_info *uv_blade_info;

extern short *uv_node_to_blade;
@@ -576,6 +576,59 @@ static inline int uv_num_possible_blades(void) 
	return uv_possible_blades;

}



/* Per Hub NMI support */

extern void uv_nmi_setup(void);



/* BMC sets a bit this MMR non-zero before sending an NMI */

#define UVH_NMI_MMR		UVH_SCRATCH5

#define UVH_NMI_MMR_CLEAR	UVH_SCRATCH5_ALIAS

#define UVH_NMI_MMR_SHIFT	63

#define	UVH_NMI_MMR_TYPE	"SCRATCH5"



/* Newer SMM NMI handler, not present in all systems */

#define UVH_NMI_MMRX		UVH_EVENT_OCCURRED0

#define UVH_NMI_MMRX_CLEAR	UVH_EVENT_OCCURRED0_ALIAS

#define UVH_NMI_MMRX_SHIFT	(is_uv1_hub() ? \

					UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT :\

					UVXH_EVENT_OCCURRED0_EXTIO_INT0_SHFT)

#define	UVH_NMI_MMRX_TYPE	"EXTIO_INT0"



/* Non-zero indicates newer SMM NMI handler present */

#define UVH_NMI_MMRX_SUPPORTED	UVH_EXTIO_INT0_BROADCAST



/* Indicates to BIOS that we want to use the newer SMM NMI handler */

#define UVH_NMI_MMRX_REQ	UVH_SCRATCH5_ALIAS_2

#define UVH_NMI_MMRX_REQ_SHIFT	62



struct uv_hub_nmi_s {

	raw_spinlock_t	nmi_lock;

	atomic_t	in_nmi;		/* flag this node in UV NMI IRQ */

	atomic_t	cpu_owner;	/* last locker of this struct */

	atomic_t	read_mmr_count;	/* count of MMR reads */

	atomic_t	nmi_count;	/* count of true UV NMIs */

	unsigned long	nmi_value;	/* last value read from NMI MMR */

};



struct uv_cpu_nmi_s {

	struct uv_hub_nmi_s	*hub;

	atomic_t		state;

	atomic_t		pinging;

	int			queries;

	int			pings;

};



DECLARE_PER_CPU(struct uv_cpu_nmi_s, __uv_cpu_nmi);

#define uv_cpu_nmi			(__get_cpu_var(__uv_cpu_nmi))

#define uv_hub_nmi			(uv_cpu_nmi.hub)

#define uv_cpu_nmi_per(cpu)		(per_cpu(__uv_cpu_nmi, cpu))

#define uv_hub_nmi_per(cpu)		(uv_cpu_nmi_per(cpu).hub)



/* uv_cpu_nmi_states */

#define	UV_NMI_STATE_OUT		0

#define	UV_NMI_STATE_IN			1

#define	UV_NMI_STATE_DUMP		2

#define	UV_NMI_STATE_DUMP_DONE		3



/* Update SCIR state */

static inline void uv_set_scir_bits(unsigned char value)

{

arch/x86/include/asm/uv/uv_mmrs.h

+31 −0
Original line number Diff line number Diff line
@@ -460,6 +460,23 @@ union uvh_event_occurred0_u { 
#define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0





/* ========================================================================= */

/*                         UVH_EXTIO_INT0_BROADCAST                          */

/* ========================================================================= */

#define UVH_EXTIO_INT0_BROADCAST 0x61448UL

#define UVH_EXTIO_INT0_BROADCAST_32 0x3f0



#define UVH_EXTIO_INT0_BROADCAST_ENABLE_SHFT		0

#define UVH_EXTIO_INT0_BROADCAST_ENABLE_MASK		0x0000000000000001UL



union uvh_extio_int0_broadcast_u {

	unsigned long	v;

	struct uvh_extio_int0_broadcast_s {

		unsigned long	enable:1;			/* RW */

		unsigned long	rsvd_1_63:63;

	} s;

};



/* ========================================================================= */

/*                         UVH_GR0_TLB_INT0_CONFIG                           */

/* ========================================================================= */
@@ -2605,6 +2622,20 @@ union uvh_scratch5_u { 
	} s;

};



/* ========================================================================= */

/*                            UVH_SCRATCH5_ALIAS                             */

/* ========================================================================= */

#define UVH_SCRATCH5_ALIAS 0x2d0208UL

#define UVH_SCRATCH5_ALIAS_32 0x780





/* ========================================================================= */

/*                           UVH_SCRATCH5_ALIAS_2                            */

/* ========================================================================= */

#define UVH_SCRATCH5_ALIAS_2 0x2d0210UL

#define UVH_SCRATCH5_ALIAS_2_32 0x788





/* ========================================================================= */

/*                          UVXH_EVENT_OCCURRED2                             */

/* ========================================================================= */

arch/x86/kernel/apic/x2apic_uv_x.c

+1 −69
Original line number Diff line number Diff line
@@ -39,12 +39,6 @@ 
#include <asm/x86_init.h>

#include <asm/nmi.h>



/* BMC sets a bit this MMR non-zero before sending an NMI */

#define UVH_NMI_MMR				UVH_SCRATCH5

#define UVH_NMI_MMR_CLEAR			(UVH_NMI_MMR + 8)

#define UV_NMI_PENDING_MASK			(1UL << 63)

DEFINE_PER_CPU(unsigned long, cpu_last_nmi_count);



DEFINE_PER_CPU(int, x2apic_extra_bits);



#define PR_DEVEL(fmt, args...)	pr_devel("%s: " fmt, __func__, args)
@@ -58,7 +52,6 @@ int uv_min_hub_revision_id; 
EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);

unsigned int uv_apicid_hibits;

EXPORT_SYMBOL_GPL(uv_apicid_hibits);

static DEFINE_SPINLOCK(uv_nmi_lock);



static struct apic apic_x2apic_uv_x;
@@ -847,68 +840,6 @@ void uv_cpu_init(void) 
		set_x2apic_extra_bits(uv_hub_info->pnode);

}



/*

 * When NMI is received, print a stack trace.

 */

int uv_handle_nmi(unsigned int reason, struct pt_regs *regs)

{

	unsigned long real_uv_nmi;

	int bid;



	/*

	 * Each blade has an MMR that indicates when an NMI has been sent

	 * to cpus on the blade. If an NMI is detected, atomically

	 * clear the MMR and update a per-blade NMI count used to

	 * cause each cpu on the blade to notice a new NMI.

	 */

	bid = uv_numa_blade_id();

	real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) & UV_NMI_PENDING_MASK);



	if (unlikely(real_uv_nmi)) {

		spin_lock(&uv_blade_info[bid].nmi_lock);

		real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) & UV_NMI_PENDING_MASK);

		if (real_uv_nmi) {

			uv_blade_info[bid].nmi_count++;

			uv_write_local_mmr(UVH_NMI_MMR_CLEAR, UV_NMI_PENDING_MASK);

		}

		spin_unlock(&uv_blade_info[bid].nmi_lock);

	}



	if (likely(__get_cpu_var(cpu_last_nmi_count) == uv_blade_info[bid].nmi_count))

		return NMI_DONE;



	__get_cpu_var(cpu_last_nmi_count) = uv_blade_info[bid].nmi_count;



	/*

	 * Use a lock so only one cpu prints at a time.

	 * This prevents intermixed output.

	 */

	spin_lock(&uv_nmi_lock);

	pr_info("UV NMI stack dump cpu %u:\n", smp_processor_id());

	dump_stack();

	spin_unlock(&uv_nmi_lock);



	return NMI_HANDLED;

}



void uv_register_nmi_notifier(void)

{

	if (register_nmi_handler(NMI_UNKNOWN, uv_handle_nmi, 0, "uv"))

		printk(KERN_WARNING "UV NMI handler failed to register\n");

}



void uv_nmi_init(void)

{

	unsigned int value;



	/*

	 * Unmask NMI on all cpus

	 */

	value = apic_read(APIC_LVT1) | APIC_DM_NMI;

	value &= ~APIC_LVT_MASKED;

	apic_write(APIC_LVT1, value);

}



void __init uv_system_init(void)

{

	union uvh_rh_gam_config_mmr_u  m_n_config;
@@ -1046,6 +977,7 @@ void __init uv_system_init(void) 
	map_mmr_high(max_pnode);

	map_mmioh_high(min_pnode, max_pnode);



	uv_nmi_setup();

	uv_cpu_init();

	uv_scir_register_cpu_notifier();

	uv_register_nmi_notifier();

arch/x86/platform/uv/Makefile

+1 −1
Original line number Diff line number Diff line 
obj-$(CONFIG_X86_UV)		+= tlb_uv.o bios_uv.o uv_irq.o uv_sysfs.o uv_time.o
 
obj-$(CONFIG_X86_UV)		+= tlb_uv.o bios_uv.o uv_irq.o uv_sysfs.o uv_time.o uv_nmi.o