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Commit 9ace9f7b authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: adjust default clock/vddc tracking for pm on DCE5 



NI chips no longer load the MC ucode in the asic_init sequence so
the asic comes up in a basic mode with low engine/memory clocks and
a voltage.  Once the MC ucode is loaded by the driver the card
can be programmed to it's proper default clocks and voltage.  As such
the default clocks in the firmware info table as the post clocks, not
the default running clocks.  Track the default post clocks and default
running clocks separately to handle this.

Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 03f40090

drivers/gpu/drm/radeon/radeon.h

+3 −0
Original line number Diff line number Diff line
@@ -823,6 +823,9 @@ struct radeon_pm { 
	u32                     current_sclk;

	u32                     current_mclk;

	u32                     current_vddc;

	u32                     default_sclk;

	u32                     default_mclk;

	u32                     default_vddc;

	struct radeon_i2c_chan *i2c_bus;

	/* selected pm method */

	enum radeon_pm_method     pm_method;

drivers/gpu/drm/radeon/radeon_atombios.c

+16 −9
Original line number Diff line number Diff line
@@ -2249,6 +2249,12 @@ static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rde 
		rdev->pm.default_power_state_index = state_index;

		rdev->pm.power_state[state_index].default_clock_mode =

			&rdev->pm.power_state[state_index].clock_info[mode_index - 1];

		if (ASIC_IS_DCE5(rdev)) {

			/* NI chips post without MC ucode, so default clocks are strobe mode only */

			rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;

			rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;

			rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;

		} else {

			/* patch the table values with the default slck/mclk from firmware info */

			for (j = 0; j < mode_index; j++) {

				rdev->pm.power_state[state_index].clock_info[j].mclk =
@@ -2261,6 +2267,7 @@ static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rde 
			}

		}

	}

}



static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,

						   int state_index, int mode_index,

drivers/gpu/drm/radeon/radeon_pm.c

+10 −8
Original line number Diff line number Diff line
@@ -167,13 +167,13 @@ static void radeon_set_power_state(struct radeon_device *rdev) 
	if (radeon_gui_idle(rdev)) {

		sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].

			clock_info[rdev->pm.requested_clock_mode_index].sclk;

		if (sclk > rdev->clock.default_sclk)

			sclk = rdev->clock.default_sclk;

		if (sclk > rdev->pm.default_sclk)

			sclk = rdev->pm.default_sclk;



		mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].

			clock_info[rdev->pm.requested_clock_mode_index].mclk;

		if (mclk > rdev->clock.default_mclk)

			mclk = rdev->clock.default_mclk;

		if (mclk > rdev->pm.default_mclk)

			mclk = rdev->pm.default_mclk;



		/* upvolt before raising clocks, downvolt after lowering clocks */

		if (sclk < rdev->pm.current_sclk)
@@ -534,8 +534,8 @@ void radeon_pm_resume(struct radeon_device *rdev) 
	mutex_lock(&rdev->pm.mutex);

	rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;

	rdev->pm.current_clock_mode_index = 0;

	rdev->pm.current_sclk = rdev->clock.default_sclk;

	rdev->pm.current_mclk = rdev->clock.default_mclk;

	rdev->pm.current_sclk = rdev->pm.default_sclk;

	rdev->pm.current_mclk = rdev->pm.default_mclk;

	rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;

	if (rdev->pm.pm_method == PM_METHOD_DYNPM

	    && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
@@ -558,6 +558,8 @@ int radeon_pm_init(struct radeon_device *rdev) 
	rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;

	rdev->pm.dynpm_can_upclock = true;

	rdev->pm.dynpm_can_downclock = true;

	rdev->pm.default_sclk = rdev->clock.default_sclk;

	rdev->pm.default_mclk = rdev->clock.default_mclk;

	rdev->pm.current_sclk = rdev->clock.default_sclk;

	rdev->pm.current_mclk = rdev->clock.default_mclk;

	rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
@@ -804,9 +806,9 @@ static int radeon_debugfs_pm_info(struct seq_file *m, void *data) 
	struct drm_device *dev = node->minor->dev;

	struct radeon_device *rdev = dev->dev_private;



	seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);

	seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);

	seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));

	seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);

	seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);

	if (rdev->asic->get_memory_clock)

		seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));

	if (rdev->pm.current_vddc)