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Commit 9a9d5c64 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nv50-nv86,nv92/mc: rearm msi via pci config space, rather than mmio mirror 



This is what NVIDIA do on these chipsets, let's hope it works around
the reported MSI failures for us on NV86.

v2: updated to include G92, as per information provided by NVIDIA.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 1b4fea0f

drivers/gpu/drm/nouveau/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -116,6 +116,7 @@ nouveau-y += core/subdev/mc/nv04.o 
nouveau-y += core/subdev/mc/nv40.o

nouveau-y += core/subdev/mc/nv44.o

nouveau-y += core/subdev/mc/nv50.o

nouveau-y += core/subdev/mc/nv94.o

nouveau-y += core/subdev/mc/nv98.o

nouveau-y += core/subdev/mc/nvc0.o

nouveau-y += core/subdev/mc/nvc3.o

drivers/gpu/drm/nouveau/core/engine/device/nv50.c

+2 −2
Original line number Diff line number Diff line
@@ -164,7 +164,7 @@ nv50_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;

		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;

		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;

		device->oclass[NVDEV_SUBDEV_MC     ] =  nv50_mc_oclass;

		device->oclass[NVDEV_SUBDEV_MC     ] =  nv94_mc_oclass;

		device->oclass[NVDEV_SUBDEV_BUS    ] = &nv50_bus_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_FB     ] = &nv50_fb_oclass;
@@ -190,7 +190,7 @@ nv50_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;

		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;

		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;

		device->oclass[NVDEV_SUBDEV_MC     ] =  nv50_mc_oclass;

		device->oclass[NVDEV_SUBDEV_MC     ] =  nv94_mc_oclass;

		device->oclass[NVDEV_SUBDEV_BUS    ] = &nv50_bus_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_FB     ] = &nv50_fb_oclass;

drivers/gpu/drm/nouveau/core/include/subdev/mc.h

+1 −0
Original line number Diff line number Diff line
@@ -48,6 +48,7 @@ extern struct nouveau_oclass *nv04_mc_oclass; 
extern struct nouveau_oclass *nv40_mc_oclass;

extern struct nouveau_oclass *nv44_mc_oclass;

extern struct nouveau_oclass *nv50_mc_oclass;

extern struct nouveau_oclass *nv94_mc_oclass;

extern struct nouveau_oclass *nv98_mc_oclass;

extern struct nouveau_oclass *nvc0_mc_oclass;

extern struct nouveau_oclass *nvc3_mc_oclass;

drivers/gpu/drm/nouveau/core/subdev/mc/nv04.h

+1 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ extern const struct nouveau_mc_intr nv04_mc_intr[]; 
int  nv04_mc_init(struct nouveau_object *);

void nv40_mc_msi_rearm(struct nouveau_mc *);

int  nv50_mc_init(struct nouveau_object *);

extern const struct nouveau_mc_intr nv50_mc_intr[];

extern const struct nouveau_mc_intr nvc0_mc_intr[];



#endif

drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c

+9 −2
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ 


#include "nv04.h"



static const struct nouveau_mc_intr

const struct nouveau_mc_intr

nv50_mc_intr[] = {

	{ 0x00000001, NVDEV_ENGINE_MPEG },

	{ 0x00000100, NVDEV_ENGINE_FIFO },
@@ -41,6 +41,13 @@ nv50_mc_intr[] = { 
	{},

};



static void

nv50_mc_msi_rearm(struct nouveau_mc *pmc)

{

	struct nouveau_device *device = nv_device(pmc);

	pci_write_config_byte(device->pdev, 0x68, 0xff);

}



int

nv50_mc_init(struct nouveau_object *object)

{
@@ -59,5 +66,5 @@ nv50_mc_oclass = &(struct nouveau_mc_oclass) { 
		.fini = _nouveau_mc_fini,

	},

	.intr = nv50_mc_intr,

	.msi_rearm = nv40_mc_msi_rearm,

	.msi_rearm = nv50_mc_msi_rearm,

}.base;