Commit 99bd0c0f authored Jun 19, 2009 by Andreas Herrmann Committed by Ingo Molnar Jun 21, 2009

x86: Set cpu_llc_id on AMD CPUs



This counts when building sched domains in case NUMA information
is not available.

( See cpu_coregroup_mask() which uses llc_shared_map which in turn is
  created based on cpu_llc_id. )

Currently Linux builds domains as follows:
(example from a dual socket quad-core system)

 CPU0 attaching sched-domain:
  domain 0: span 0-7 level CPU
   groups: 0 1 2 3 4 5 6 7

  ...

 CPU7 attaching sched-domain:
  domain 0: span 0-7 level CPU
   groups: 7 0 1 2 3 4 5 6

Ever since that is borked for multi-core AMD CPU systems.
This patch fixes that and now we get a proper:

 CPU0 attaching sched-domain:
  domain 0: span 0-3 level MC
   groups: 0 1 2 3
   domain 1: span 0-7 level CPU
    groups: 0-3 4-7

  ...

 CPU7 attaching sched-domain:
  domain 0: span 4-7 level MC
   groups: 7 4 5 6
   domain 1: span 0-7 level CPU
    groups: 4-7 0-3

This allows scheduler to assign tasks to cores on different sockets
(i.e. that don't share last level cache) for performance reasons.

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
LKML-Reference: <20090619085909.GJ5218@alberich.amd.com>
Cc: <stable@kernel.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

parent c277331d

arch/x86/kernel/cpu/amd.c

+3 −1

Original line number	Diff line number	Diff line
		@@ -258,13 +258,15 @@ static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
		{
		#ifdef CONFIG_X86_HT
		unsigned bits;
		int cpu = smp_processor_id();

		bits = c->x86_coreid_bits;

		/* Low order bits define the core id (index of core in socket) */
		c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
		/* Convert the initial APIC ID into the socket ID */
		c->phys_proc_id = c->initial_apicid >> bits;
		/* use socket ID also for last level cache */
		per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
		#endif
		}