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Commit 99b13116 authored by Konrad Rzeszutek Wilk's avatar Konrad Rzeszutek Wilk Committed by Greg Kroah-Hartman
Browse files

x86/bugs: Whitelist allowed SPEC_CTRL MSR values 



commit 1115a859f33276fe8afb31c60cf9d8e657872558 upstream

Intel and AMD SPEC_CTRL (0x48) MSR semantics may differ in the
future (or in fact use different MSRs for the same functionality).

As such a run-time mechanism is required to whitelist the appropriate MSR
values.

[ tglx: Made the variable __ro_after_init ]

Signed-off-by: default avatarKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Reviewed-by: default avatarIngo Molnar <mingo@kernel.org>
Signed-off-by: default avatarDavid Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 19e3a2be

arch/x86/kernel/cpu/bugs.c

+9 −2
Original line number Diff line number Diff line
@@ -34,6 +34,12 @@ static void __init ssb_select_mitigation(void); 
 */

static u64 __ro_after_init x86_spec_ctrl_base;



/*

 * The vendor and possibly platform specific bits which can be modified in

 * x86_spec_ctrl_base.

 */

static u64 __ro_after_init x86_spec_ctrl_mask = ~SPEC_CTRL_IBRS;



void __init check_bugs(void)

{

	identify_boot_cpu();
@@ -116,7 +122,7 @@ static enum spectre_v2_mitigation spectre_v2_enabled = SPECTRE_V2_NONE; 


void x86_spec_ctrl_set(u64 val)

{

	if (val & ~(SPEC_CTRL_IBRS | SPEC_CTRL_RDS))

	if (val & x86_spec_ctrl_mask)

		WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val);

	else

		wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base | val);
@@ -458,6 +464,7 @@ static enum ssb_mitigation_cmd __init __ssb_select_mitigation(void) 
		switch (boot_cpu_data.x86_vendor) {

		case X86_VENDOR_INTEL:

			x86_spec_ctrl_base |= SPEC_CTRL_RDS;

			x86_spec_ctrl_mask &= ~SPEC_CTRL_RDS;

			x86_spec_ctrl_set(SPEC_CTRL_RDS);

			break;

		case X86_VENDOR_AMD:
@@ -481,7 +488,7 @@ static void ssb_select_mitigation() 
void x86_spec_ctrl_setup_ap(void)

{

	if (boot_cpu_has(X86_FEATURE_IBRS))

		x86_spec_ctrl_set(x86_spec_ctrl_base & (SPEC_CTRL_IBRS | SPEC_CTRL_RDS));

		x86_spec_ctrl_set(x86_spec_ctrl_base & ~x86_spec_ctrl_mask);

}



#ifdef CONFIG_SYSFS