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Commit 990c70ad authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/powerplay: fix issue can't enable vce dpm. 



Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: default avatarEric Huang <JinhuiEric.Huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ec38f188

drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c

+11 −3
Original line number Diff line number Diff line
@@ -131,11 +131,19 @@ int polaris10_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) 


	data->vce_power_gated = bgate;



	if (bgate)

	if (bgate) {

		cgs_set_clockgating_state(hwmgr->device,

				AMD_IP_BLOCK_TYPE_VCE,

				AMD_CG_STATE_GATE);

		polaris10_update_vce_dpm(hwmgr, true);

		polaris10_phm_powerdown_vce(hwmgr);

	else

	} else {

		polaris10_phm_powerup_vce(hwmgr);



		polaris10_update_vce_dpm(hwmgr, false);

		cgs_set_clockgating_state(hwmgr->device,

				AMD_IP_BLOCK_TYPE_VCE,

				AMD_CG_STATE_UNGATE);

	}

	return 0;

}

drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c

+10 −24
Original line number Diff line number Diff line
@@ -4424,25 +4424,20 @@ int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate) 
	return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate);

}



static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)

int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, bool bgate)

{

	const struct phm_set_power_state_input *states =

			(const struct phm_set_power_state_input *)input;

	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);

	const struct polaris10_power_state *polaris10_nps =

			cast_const_phw_polaris10_power_state(states->pnew_state);

	const struct polaris10_power_state *polaris10_cps =

			cast_const_phw_polaris10_power_state(states->pcurrent_state);



	uint32_t mm_boot_level_offset, mm_boot_level_value;

	struct phm_ppt_v1_information *table_info =

			(struct phm_ppt_v1_information *)(hwmgr->pptable);



	if (polaris10_nps->vce_clks.evclk > 0 &&

	(polaris10_cps == NULL || polaris10_cps->vce_clks.evclk == 0)) {



	if (!bgate) {

		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,

						PHM_PlatformCaps_StablePState))

			data->smc_state_table.VceBootLevel =

				(uint8_t) (table_info->mm_dep_table->count - 1);

		else

			data->smc_state_table.VceBootLevel = 0;



		mm_boot_level_offset = data->dpm_table_start +

				offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
@@ -4455,18 +4450,14 @@ static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input) 
		cgs_write_ind_register(hwmgr->device,

				CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);



		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {

		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))

			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,

					PPSMC_MSG_VCEDPM_SetEnabledMask,

					(uint32_t)1 << data->smc_state_table.VceBootLevel);



			polaris10_enable_disable_vce_dpm(hwmgr, true);

		} else if (polaris10_nps->vce_clks.evclk == 0 &&

				polaris10_cps != NULL &&

				polaris10_cps->vce_clks.evclk > 0)

			polaris10_enable_disable_vce_dpm(hwmgr, false);

	}



	polaris10_enable_disable_vce_dpm(hwmgr, !bgate);



	return 0;

}
@@ -4655,11 +4646,6 @@ static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *i 
			"Failed to generate DPM level enabled mask!",

			result = tmp_result);



	tmp_result = polaris10_update_vce_dpm(hwmgr, input);

	PP_ASSERT_WITH_CODE((0 == tmp_result),

			"Failed to update VCE DPM!",

			result = tmp_result);



	tmp_result = polaris10_update_sclk_threshold(hwmgr);

	PP_ASSERT_WITH_CODE((0 == tmp_result),

			"Failed to update SCLK threshold!",

drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h

+1 −1
Original line number Diff line number Diff line
@@ -352,6 +352,6 @@ int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr); 
int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);

int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate);

int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);



int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, bool bgate);

#endif