Loading arch/mips/kernel/traps.c +1 −0 Original line number Original line Diff line number Diff line Loading @@ -902,6 +902,7 @@ static inline void parity_protection_init(void) { { switch (current_cpu_data.cputype) { switch (current_cpu_data.cputype) { case CPU_24K: case CPU_24K: case CPU_34K: case CPU_5KC: case CPU_5KC: write_c0_ecc(0x80000000); write_c0_ecc(0x80000000); back_to_back_c0_hazard(); back_to_back_c0_hazard(); Loading arch/mips/mm/c-r4k.c +1 −0 Original line number Original line Diff line number Diff line Loading @@ -968,6 +968,7 @@ static void __init probe_pcache(void) case CPU_SB1: case CPU_SB1: break; break; case CPU_24K: case CPU_24K: case CPU_34K: if (!(read_c0_config7() & (1 << 16))) if (!(read_c0_config7() & (1 << 16))) default: default: if (c->dcache.waysize > PAGE_SIZE) if (c->dcache.waysize > PAGE_SIZE) Loading Loading
arch/mips/kernel/traps.c +1 −0 Original line number Original line Diff line number Diff line Loading @@ -902,6 +902,7 @@ static inline void parity_protection_init(void) { { switch (current_cpu_data.cputype) { switch (current_cpu_data.cputype) { case CPU_24K: case CPU_24K: case CPU_34K: case CPU_5KC: case CPU_5KC: write_c0_ecc(0x80000000); write_c0_ecc(0x80000000); back_to_back_c0_hazard(); back_to_back_c0_hazard(); Loading
arch/mips/mm/c-r4k.c +1 −0 Original line number Original line Diff line number Diff line Loading @@ -968,6 +968,7 @@ static void __init probe_pcache(void) case CPU_SB1: case CPU_SB1: break; break; case CPU_24K: case CPU_24K: case CPU_34K: if (!(read_c0_config7() & (1 << 16))) if (!(read_c0_config7() & (1 << 16))) default: default: if (c->dcache.waysize > PAGE_SIZE) if (c->dcache.waysize > PAGE_SIZE) Loading