Merge remote-tracking branches 'asoc/topic/doc', 'asoc/topic/dwc',... (97edc416) · Commits · e / devices / android_kernel_teracube_2e

Documentation/devicetree/bindings/sound/designware-i2s.txt

0 → 100644

+31 −0

Original line number	Diff line number	Diff line
		DesignWare I2S controller

		Required properties:
		- compatible : Must be "snps,designware-i2s"
		- reg : Must contain the I2S core's registers location and length
		- clocks : Pairs of phandle and specifier referencing the controller's
		clocks. The controller expects one clock: the clock used as the sampling
		rate reference clock sample.
		- clock-names : "i2sclk" for the sample rate reference clock.
		- dmas: Pairs of phandle and specifier for the DMA channels that are used by
		the core. The core expects one or two dma channels: one for transmit and
		one for receive.
		- dma-names : "tx" for the transmit channel, "rx" for the receive channel.

		For more details on the 'dma', 'dma-names', 'clock' and 'clock-names'
		properties please check:
		* resource-names.txt
		* clock/clock-bindings.txt
		* dma/dma.txt

		Example:

		soc_i2s: i2s@7ff90000 {
		compatible = "snps,designware-i2s";
		reg = <0x0 0x7ff90000 0x0 0x1000>;
		clocks = <&scpi_i2sclk 0>;
		clock-names = "i2sclk";
		#sound-dai-cells = <0>;
		dmas = <&dma0 5>;
		dma-names = "tx";
		};

sound/soc/dwc/Kconfig

+1 −0

Original line number	Diff line number	Diff line
		config SND_DESIGNWARE_I2S
		tristate "Synopsys I2S Device Driver"
		depends on CLKDEV_LOOKUP
		select SND_SOC_GENERIC_DMAENGINE_PCM
		help
		Say Y or M if you want to add support for I2S driver for
		Synopsys desigwnware I2S device. The device supports upto

sound/soc/dwc/designware_i2s.c

+229 −52

Original line number	Diff line number	Diff line
		@@ -22,6 +22,7 @@
		#include <sound/pcm.h>
		#include <sound/pcm_params.h>
		#include <sound/soc.h>
		#include <sound/dmaengine_pcm.h>

		/* common register for all channel */
		#define IER 0x000
		@@ -54,9 +55,39 @@
		#define I2S_COMP_VERSION 0x01F8
		#define I2S_COMP_TYPE 0x01FC

		/*
		* Component parameter register fields - define the I2S block's
		* configuration.
		*/
		#define COMP1_TX_WORDSIZE_3(r) (((r) & GENMASK(27, 25)) >> 25)
		#define COMP1_TX_WORDSIZE_2(r) (((r) & GENMASK(24, 22)) >> 22)
		#define COMP1_TX_WORDSIZE_1(r) (((r) & GENMASK(21, 19)) >> 19)
		#define COMP1_TX_WORDSIZE_0(r) (((r) & GENMASK(18, 16)) >> 16)
		#define COMP1_TX_CHANNELS(r) (((r) & GENMASK(10, 9)) >> 9)
		#define COMP1_RX_CHANNELS(r) (((r) & GENMASK(8, 7)) >> 7)
		#define COMP1_RX_ENABLED(r) (((r) & BIT(6)) >> 6)
		#define COMP1_TX_ENABLED(r) (((r) & BIT(5)) >> 5)
		#define COMP1_MODE_EN(r) (((r) & BIT(4)) >> 4)
		#define COMP1_FIFO_DEPTH_GLOBAL(r) (((r) & GENMASK(3, 2)) >> 2)
		#define COMP1_APB_DATA_WIDTH(r) (((r) & GENMASK(1, 0)) >> 0)

		#define COMP2_RX_WORDSIZE_3(r) (((r) & GENMASK(12, 10)) >> 10)
		#define COMP2_RX_WORDSIZE_2(r) (((r) & GENMASK(9, 7)) >> 7)
		#define COMP2_RX_WORDSIZE_1(r) (((r) & GENMASK(5, 3)) >> 3)
		#define COMP2_RX_WORDSIZE_0(r) (((r) & GENMASK(2, 0)) >> 0)

		/* Number of entries in WORDSIZE and DATA_WIDTH parameter registers */
		#define COMP_MAX_WORDSIZE (1 << 3)
		#define COMP_MAX_DATA_WIDTH (1 << 2)

		#define MAX_CHANNEL_NUM 8
		#define MIN_CHANNEL_NUM 2

		union dw_i2s_snd_dma_data {
		struct i2s_dma_data pd;
		struct snd_dmaengine_dai_dma_data dt;
		};

		struct dw_i2s_dev {
		void __iomem *i2s_base;
		struct clk *clk;
		@@ -65,8 +96,8 @@ struct dw_i2s_dev {
		struct device *dev;

		/* data related to DMA transfers b/w i2s and DMAC */
		struct i2s_dma_data play_dma_data;
		struct i2s_dma_data capture_dma_data;
		union dw_i2s_snd_dma_data play_dma_data;
		union dw_i2s_snd_dma_data capture_dma_data;
		struct i2s_clk_config_data config;
		int (i2s_clk_cfg)(struct i2s_clk_config_data config);
		};
		@@ -153,7 +184,7 @@ static int dw_i2s_startup(struct snd_pcm_substream *substream,
		struct snd_soc_dai *cpu_dai)
		{
		struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
		struct i2s_dma_data *dma_data = NULL;
		union dw_i2s_snd_dma_data *dma_data = NULL;

		if (!(dev->capability & DWC_I2S_RECORD) &&
		(substream->stream == SNDRV_PCM_STREAM_CAPTURE))
		@@ -242,14 +273,22 @@ static int dw_i2s_hw_params(struct snd_pcm_substream *substream,

		config->sample_rate = params_rate(params);

		if (!dev->i2s_clk_cfg)
		return -EINVAL;

		if (dev->i2s_clk_cfg) {
		ret = dev->i2s_clk_cfg(config);
		if (ret < 0) {
		dev_err(dev->dev, "runtime audio clk config fail\n");
		return ret;
		}
		} else {
		u32 bitclk = config->sample_rate * config->data_width * 2;

		ret = clk_set_rate(dev->clk, bitclk);
		if (ret) {
		dev_err(dev->dev, "Can't set I2S clock rate: %d\n",
		ret);
		return ret;
		}
		}

		return 0;
		}
		@@ -335,39 +374,152 @@ static int dw_i2s_resume(struct snd_soc_dai *dai)
		#define dw_i2s_resume NULL
		#endif

		static void dw_configure_dai_by_pd(struct dw_i2s_dev *dev,
		/*
		* The following tables allow a direct lookup of various parameters
		* defined in the I2S block's configuration in terms of sound system
		* parameters. Each table is sized to the number of entries possible
		* according to the number of configuration bits describing an I2S
		* block parameter.
		*/

		/* Maximum bit resolution of a channel - not uniformly spaced */
		static const u32 fifo_width[COMP_MAX_WORDSIZE] = {
		12, 16, 20, 24, 32, 0, 0, 0
		};

		/* Width of (DMA) bus */
		static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = {
		DMA_SLAVE_BUSWIDTH_1_BYTE,
		DMA_SLAVE_BUSWIDTH_2_BYTES,
		DMA_SLAVE_BUSWIDTH_4_BYTES,
		DMA_SLAVE_BUSWIDTH_UNDEFINED
		};

		/* PCM format to support channel resolution */
		static const u32 formats[COMP_MAX_WORDSIZE] = {
		SNDRV_PCM_FMTBIT_S16_LE,
		SNDRV_PCM_FMTBIT_S16_LE,
		SNDRV_PCM_FMTBIT_S24_LE,
		SNDRV_PCM_FMTBIT_S24_LE,
		SNDRV_PCM_FMTBIT_S32_LE,
		0,
		0,
		0
		};

		static int dw_configure_dai(struct dw_i2s_dev *dev,
		struct snd_soc_dai_driver *dw_i2s_dai,
		struct resource *res,
		const struct i2s_platform_data *pdata)
		unsigned int rates)
		{
		/* Set DMA slaves info */
		/*
		* Read component parameter registers to extract
		* the I2S block's configuration.
		*/
		u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
		u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);
		u32 idx;

		dev->play_dma_data.data = pdata->play_dma_data;
		dev->capture_dma_data.data = pdata->capture_dma_data;
		dev->play_dma_data.addr = res->start + I2S_TXDMA;
		dev->capture_dma_data.addr = res->start + I2S_RXDMA;
		dev->play_dma_data.max_burst = 16;
		dev->capture_dma_data.max_burst = 16;
		dev->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
		dev->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
		dev->play_dma_data.filter = pdata->filter;
		dev->capture_dma_data.filter = pdata->filter;

		if (pdata->cap & DWC_I2S_PLAY) {
		if (COMP1_TX_ENABLED(comp1)) {
		dev_dbg(dev->dev, " designware: play supported\n");
		idx = COMP1_TX_WORDSIZE_0(comp1);
		if (WARN_ON(idx >= ARRAY_SIZE(formats)))
		return -EINVAL;
		dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM;
		dw_i2s_dai->playback.channels_max = pdata->channel;
		dw_i2s_dai->playback.formats = pdata->snd_fmts;
		dw_i2s_dai->playback.rates = pdata->snd_rates;
		dw_i2s_dai->playback.channels_max =
		1 << (COMP1_TX_CHANNELS(comp1) + 1);
		dw_i2s_dai->playback.formats = formats[idx];
		dw_i2s_dai->playback.rates = rates;
		}

		if (pdata->cap & DWC_I2S_RECORD) {
		if (COMP1_RX_ENABLED(comp1)) {
		dev_dbg(dev->dev, "designware: record supported\n");
		idx = COMP2_RX_WORDSIZE_0(comp2);
		if (WARN_ON(idx >= ARRAY_SIZE(formats)))
		return -EINVAL;
		dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM;
		dw_i2s_dai->capture.channels_max = pdata->channel;
		dw_i2s_dai->capture.formats = pdata->snd_fmts;
		dw_i2s_dai->capture.rates = pdata->snd_rates;
		dw_i2s_dai->capture.channels_max =
		1 << (COMP1_RX_CHANNELS(comp1) + 1);
		dw_i2s_dai->capture.formats = formats[idx];
		dw_i2s_dai->capture.rates = rates;
		}

		return 0;
		}

		static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev,
		struct snd_soc_dai_driver *dw_i2s_dai,
		struct resource *res,
		const struct i2s_platform_data *pdata)
		{
		u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
		u32 idx = COMP1_APB_DATA_WIDTH(comp1);
		int ret;

		if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
		return -EINVAL;

		ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates);
		if (ret < 0)
		return ret;

		/* Set DMA slaves info */
		dev->play_dma_data.pd.data = pdata->play_dma_data;
		dev->capture_dma_data.pd.data = pdata->capture_dma_data;
		dev->play_dma_data.pd.addr = res->start + I2S_TXDMA;
		dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA;
		dev->play_dma_data.pd.max_burst = 16;
		dev->capture_dma_data.pd.max_burst = 16;
		dev->play_dma_data.pd.addr_width = bus_widths[idx];
		dev->capture_dma_data.pd.addr_width = bus_widths[idx];
		dev->play_dma_data.pd.filter = pdata->filter;
		dev->capture_dma_data.pd.filter = pdata->filter;

		return 0;
		}

		static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev,
		struct snd_soc_dai_driver *dw_i2s_dai,
		struct resource *res)
		{
		u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
		u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);
		u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
		u32 idx = COMP1_APB_DATA_WIDTH(comp1);
		u32 idx2;
		int ret;

		if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
		return -EINVAL;

		ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000);
		if (ret < 0)
		return ret;

		if (COMP1_TX_ENABLED(comp1)) {
		idx2 = COMP1_TX_WORDSIZE_0(comp1);

		dev->capability \|= DWC_I2S_PLAY;
		dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;
		dev->play_dma_data.dt.addr_width = bus_widths[idx];
		dev->play_dma_data.dt.chan_name = "TX";
		dev->play_dma_data.dt.fifo_size = fifo_depth *
		(fifo_width[idx2]) >> 8;
		dev->play_dma_data.dt.maxburst = 16;
		}
		if (COMP1_RX_ENABLED(comp1)) {
		idx2 = COMP2_RX_WORDSIZE_0(comp2);

		dev->capability \|= DWC_I2S_RECORD;
		dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;
		dev->capture_dma_data.dt.addr_width = bus_widths[idx];
		dev->capture_dma_data.dt.chan_name = "RX";
		dev->capture_dma_data.dt.fifo_size = fifo_depth *
		(fifo_width[idx2] >> 8);
		dev->capture_dma_data.dt.maxburst = 16;
		}

		return 0;

		}

		static int dw_i2s_probe(struct platform_device *pdev)
		@@ -378,11 +530,6 @@ static int dw_i2s_probe(struct platform_device *pdev)
		int ret;
		struct snd_soc_dai_driver *dw_i2s_dai;

		if (!pdata) {
		dev_err(&pdev->dev, "Invalid platform data\n");
		return -EINVAL;
		}

		dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
		if (!dev) {
		dev_warn(&pdev->dev, "kzalloc fail\n");
		@@ -403,32 +550,54 @@ static int dw_i2s_probe(struct platform_device *pdev)
		return PTR_ERR(dev->i2s_base);

		dev->dev = &pdev->dev;
		dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata);
		if (pdata) {
		ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata);
		if (ret < 0)
		return ret;

		dev->capability = pdata->cap;
		dev->i2s_clk_cfg = pdata->i2s_clk_cfg;
		dev->clk = clk_get(&pdev->dev, NULL);
		if (!dev->i2s_clk_cfg) {
		dev_err(&pdev->dev, "no clock configure method\n");
		return -ENODEV;
		}

		dev->clk = devm_clk_get(&pdev->dev, NULL);
		} else {
		ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res);
		if (ret < 0)
		return ret;

		dev->clk = devm_clk_get(&pdev->dev, "i2sclk");
		}
		if (IS_ERR(dev->clk))
		return PTR_ERR(dev->clk);

		ret = clk_enable(dev->clk);
		ret = clk_prepare_enable(dev->clk);
		if (ret < 0)
		goto err_clk_put;
		return ret;

		dev_set_drvdata(&pdev->dev, dev);
		ret = snd_soc_register_component(&pdev->dev, &dw_i2s_component,
		ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component,
		dw_i2s_dai, 1);
		if (ret != 0) {
		dev_err(&pdev->dev, "not able to register dai\n");
		goto err_clk_disable;
		}

		if (!pdata) {
		ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
		if (ret) {
		dev_err(&pdev->dev,
		"Could not register PCM: %d\n", ret);
		goto err_clk_disable;
		}
		}

		return 0;

		err_clk_disable:
		clk_disable(dev->clk);
		err_clk_put:
		clk_put(dev->clk);
		clk_disable_unprepare(dev->clk);
		return ret;
		}

		@@ -436,18 +605,26 @@ static int dw_i2s_remove(struct platform_device *pdev)
		{
		struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev);

		snd_soc_unregister_component(&pdev->dev);

		clk_put(dev->clk);
		clk_disable_unprepare(dev->clk);

		return 0;
		}

		#ifdef CONFIG_OF
		static const struct of_device_id dw_i2s_of_match[] = {
		{ .compatible = "snps,designware-i2s", },
		{},
		};

		MODULE_DEVICE_TABLE(of, dw_i2s_of_match);
		#endif

		static struct platform_driver dw_i2s_driver = {
		.probe = dw_i2s_probe,
		.remove = dw_i2s_remove,
		.driver = {
		.name = "designware-i2s",
		.of_match_table = of_match_ptr(dw_i2s_of_match),
		},
		};

sound/soc/fsl/fsl_asrc.c

+2 −3

Original line number	Diff line number	Diff line
		@@ -818,7 +818,6 @@ static int fsl_asrc_probe(struct platform_device *pdev)
		return -ENOMEM;

		asrc_priv->pdev = pdev;
		strncpy(asrc_priv->name, np->name, sizeof(asrc_priv->name) - 1);

		/* Get the addresses and IRQ */
		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		@@ -837,12 +836,12 @@ static int fsl_asrc_probe(struct platform_device *pdev)

		irq = platform_get_irq(pdev, 0);
		if (irq < 0) {
		dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
		dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
		return irq;
		}

		ret = devm_request_irq(&pdev->dev, irq, fsl_asrc_isr, 0,
		asrc_priv->name, asrc_priv);
		dev_name(&pdev->dev), asrc_priv);
		if (ret) {
		dev_err(&pdev->dev, "failed to claim irq %u: %d\n", irq, ret);
		return ret;

sound/soc/fsl/fsl_asrc.h

+0 −3

Original line number	Diff line number	Diff line
		@@ -433,7 +433,6 @@ struct fsl_asrc_pair {
		* @channel_avail: non-occupied channel numbers
		* @asrc_rate: default sample rate for ASoC Back-Ends
		* @asrc_width: default sample width for ASoC Back-Ends
		* @name: driver name
		*/
		struct fsl_asrc {
		struct snd_dmaengine_dai_dma_data dma_params_rx;
		@@ -452,8 +451,6 @@ struct fsl_asrc {

		int asrc_rate;
		int asrc_width;

		char name[32];
		};

		extern struct snd_soc_platform_driver fsl_asrc_platform;