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Commit 97c24c1a authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge branches 'cross-platform/debug_ll' and 'cross-platform/cpu-mapping' into next/cross-platform

parents f350b861 4a139b64

arch/arm/Kconfig

+25 −0
Original line number Diff line number Diff line
@@ -1393,6 +1393,31 @@ config SMP_ON_UP 


	  If you don't know what to do here, say Y.



config ARM_CPU_TOPOLOGY

	bool "Support cpu topology definition"

	depends on SMP && CPU_V7

	default y

	help

	  Support ARM cpu topology definition. The MPIDR register defines

	  affinity between processors which is then used to describe the cpu

	  topology of an ARM System.



config SCHED_MC

	bool "Multi-core scheduler support"

	depends on ARM_CPU_TOPOLOGY

	help

	  Multi-core scheduler support improves the CPU scheduler's decision

	  making when dealing with multi-core CPU chips at a cost of slightly

	  increased overhead in some places. If unsure say N here.



config SCHED_SMT

	bool "SMT scheduler support"

	depends on ARM_CPU_TOPOLOGY

	help

	  Improves the CPU scheduler's decision making when dealing with

	  MultiThreading at a cost of slightly increased overhead in some

	  places. If unsure say N here.



config HAVE_ARM_SCU

	bool

	help

arch/arm/common/gic.c

+14 −3
Original line number Diff line number Diff line
@@ -180,7 +180,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 
		return -EINVAL;



	mask = 0xff << shift;

	bit = 1 << (cpu + shift);

	bit = 1 << (cpu_logical_map(cpu) + shift);



	spin_lock(&irq_controller_lock);

	val = readl_relaxed(reg) & ~mask;
@@ -259,9 +259,15 @@ static void __init gic_dist_init(struct gic_chip_data *gic, 
	unsigned int irq_start)

{

	unsigned int gic_irqs, irq_limit, i;

	u32 cpumask;

	void __iomem *base = gic->dist_base;

	u32 cpumask = 1 << smp_processor_id();

	u32 cpu = 0;



#ifdef CONFIG_SMP

	cpu = cpu_logical_map(smp_processor_id());

#endif



	cpumask = 1 << cpu;

	cpumask |= cpumask << 8;

	cpumask |= cpumask << 16;
@@ -382,7 +388,12 @@ void __cpuinit gic_enable_ppi(unsigned int irq) 
#ifdef CONFIG_SMP

void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)

{

	unsigned long map = *cpus_addr(*mask);

	int cpu;

	unsigned long map = 0;



	/* Convert our logical CPU mask into a physical one. */

	for_each_cpu(cpu, mask)

		map |= 1 << cpu_logical_map(cpu);



	/*

	 * Ensure that stores to Normal memory are visible to the

arch/arm/include/asm/cputype.h

+6 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
#define CPUID_CACHETYPE	1

#define CPUID_TCM	2

#define CPUID_TLBTYPE	3

#define CPUID_MPIDR	5



#define CPUID_EXT_PFR0	"c1, 0"

#define CPUID_EXT_PFR1	"c1, 1"
@@ -70,6 +71,11 @@ static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void) 
	return read_cpuid(CPUID_TCM);

}



static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)

{

	return read_cpuid(CPUID_MPIDR);

}



/*

 * Intel's XScale3 core supports some v6 features (supersections, L2)

 * but advertises itself as v5 as it does not support the v6 ISA.  For

arch/arm/include/asm/exception.h

0 → 100644
+19 −0
Original line number Diff line number Diff line 
/*

 * Annotations for marking C functions as exception handlers.

 *

 * These should only be used for C functions that are called from the low

 * level exception entry code and not any intervening C code.

 */

#ifndef __ASM_ARM_EXCEPTION_H

#define __ASM_ARM_EXCEPTION_H



#include <linux/ftrace.h>



#define __exception	__attribute__((section(".exception.text")))

#ifdef CONFIG_FUNCTION_GRAPH_TRACER

#define __exception_irq_entry	__irq_entry

#else

#define __exception_irq_entry	__exception

#endif



#endif /* __ASM_ARM_EXCEPTION_H */

arch/arm/include/asm/localtimer.h

+4 −0
Original line number Diff line number Diff line
@@ -22,6 +22,10 @@ void percpu_timer_setup(void); 
 */

asmlinkage void do_local_timer(struct pt_regs *);



/*

 * Called from C code

 */

void handle_local_timer(struct pt_regs *);



#ifdef CONFIG_LOCAL_TIMERS