Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 97ac8cae authored by Bruce Allan's avatar Bruce Allan Committed by Jeff Garzik
Browse files

e1000e: Add support for BM PHYs on ICH9 

This patch adds support for the BM PHY, a new PHY model being used
on ICH9-based implementations.

This new PHY exposes issues in the ICH9 silicon when receiving
jumbo frames large enough to use more than a certain part of the
Rx FIFO, and this unfortunately breaks packet split jumbo receives.
For this reason we re-introduce (for affected adapters only) the
jumbo single-skb receive routine back so that people who do
wish to use jumbo frames on these ich9 platforms can do so.
Part of this problem has to do with CPU sleep states and to make
sure that all the wake up timings are correctly we force them
with the recently merged pm_qos infrastructure written by Mark
Gross. (See http://lkml.org/lkml/2007/10/4/400

).

To make code read a bit easier we introduce a _IS_ICH flag so
that we don't need to do mac type checks over the code.

Signed-off-by: default avatarBruce Allan <bruce.w.allan@intel.com>
Signed-off-by: default avatarAuke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: default avatarJeff Garzik <jgarzik@redhat.com>
parent e284e5c6

drivers/net/e1000e/defines.h

+10 −0
Original line number Diff line number Diff line
@@ -648,6 +648,8 @@ 
#define IFE_E_PHY_ID         0x02A80330

#define IFE_PLUS_E_PHY_ID    0x02A80320

#define IFE_C_E_PHY_ID       0x02A80310

#define BME1000_E_PHY_ID     0x01410CB0

#define BME1000_E_PHY_ID_R2  0x01410CB1



/* M88E1000 Specific Registers */

#define M88E1000_PHY_SPEC_CTRL     0x10  /* PHY Specific Control Register */
@@ -701,6 +703,14 @@ 
#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK  0x0E00

#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X    0x0800



/* BME1000 PHY Specific Control Register */

#define BME1000_PSCR_ENABLE_DOWNSHIFT   0x0800 /* 1 = enable downshift */





#define PHY_PAGE_SHIFT 5

#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \

                           ((reg) & MAX_PHY_REG_ADDRESS))



/*

 * Bits...

 * 15-5: page

drivers/net/e1000e/e1000.h

+6 −1
Original line number Diff line number Diff line
@@ -127,7 +127,7 @@ struct e1000_buffer { 
		/* arrays of page information for packet split */

		struct e1000_ps_page *ps_pages;

	};



	struct page *page;

};



struct e1000_ring {
@@ -304,6 +304,7 @@ struct e1000_info { 
#define FLAG_HAS_CTRLEXT_ON_LOAD          (1 << 5)

#define FLAG_HAS_SWSM_ON_LOAD             (1 << 6)

#define FLAG_HAS_JUMBO_FRAMES             (1 << 7)

#define FLAG_IS_ICH                       (1 << 9)

#define FLAG_HAS_SMART_POWER_DOWN         (1 << 11)

#define FLAG_IS_QUAD_PORT_A               (1 << 12)

#define FLAG_IS_QUAD_PORT                 (1 << 13)
@@ -386,6 +387,7 @@ extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 
						 bool state);

extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);

extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);

extern void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw);



extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw);

extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
@@ -443,6 +445,9 @@ extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw); 
extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);

extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);

extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);

extern s32 e1000e_determine_phy_address(struct e1000_hw *hw);

extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);

extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);

extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);

extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);

extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);

drivers/net/e1000e/ethtool.c

+28 −11
Original line number Diff line number Diff line
@@ -803,8 +803,7 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data) 
	/* restore previous status */

	ew32(STATUS, before);



	if ((mac->type != e1000_ich8lan) &&

	    (mac->type != e1000_ich9lan)) {

	if (!(adapter->flags & FLAG_IS_ICH)) {

		REG_PATTERN_TEST(E1000_FCAL, 0xFFFFFFFF, 0xFFFFFFFF);

		REG_PATTERN_TEST(E1000_FCAH, 0x0000FFFF, 0xFFFFFFFF);

		REG_PATTERN_TEST(E1000_FCT, 0x0000FFFF, 0xFFFFFFFF);
@@ -824,15 +823,13 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data) 


	REG_SET_AND_CHECK(E1000_RCTL, 0xFFFFFFFF, 0x00000000);



	before = (((mac->type == e1000_ich8lan) ||

		   (mac->type == e1000_ich9lan)) ? 0x06C3B33E : 0x06DFB3FE);

	before = ((adapter->flags & FLAG_IS_ICH) ? 0x06C3B33E : 0x06DFB3FE);

	REG_SET_AND_CHECK(E1000_RCTL, before, 0x003FFFFB);

	REG_SET_AND_CHECK(E1000_TCTL, 0xFFFFFFFF, 0x00000000);



	REG_SET_AND_CHECK(E1000_RCTL, before, 0xFFFFFFFF);

	REG_PATTERN_TEST(E1000_RDBAL, 0xFFFFFFF0, 0xFFFFFFFF);

	if ((mac->type != e1000_ich8lan) &&

	    (mac->type != e1000_ich9lan))

	if (!(adapter->flags & FLAG_IS_ICH))

		REG_PATTERN_TEST(E1000_TXCW, 0xC000FFFF, 0x0000FFFF);

	REG_PATTERN_TEST(E1000_TDBAL, 0xFFFFFFF0, 0xFFFFFFFF);

	REG_PATTERN_TEST(E1000_TIDV, 0x0000FFFF, 0x0000FFFF);
@@ -911,9 +908,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data) 


	/* Test each interrupt */

	for (i = 0; i < 10; i++) {



		if (((adapter->hw.mac.type == e1000_ich8lan) ||

		     (adapter->hw.mac.type == e1000_ich9lan)) && i == 8)

		if ((adapter->flags & FLAG_IS_ICH) && (i == 8))

			continue;



		/* Interrupt to test */
@@ -1184,6 +1179,7 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter) 
	struct e1000_hw *hw = &adapter->hw;

	u32 ctrl_reg = 0;

	u32 stat_reg = 0;

	u16 phy_reg = 0;



	hw->mac.autoneg = 0;
@@ -1211,6 +1207,28 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter) 
			     E1000_CTRL_SPD_100 |/* Force Speed to 100 */

			     E1000_CTRL_FD);	 /* Force Duplex to FULL */

		break;

	case e1000_phy_bm:

		/* Set Default MAC Interface speed to 1GB */

		e1e_rphy(hw, PHY_REG(2, 21), &phy_reg);

		phy_reg &= ~0x0007;

		phy_reg |= 0x006;

		e1e_wphy(hw, PHY_REG(2, 21), phy_reg);

		/* Assert SW reset for above settings to take effect */

		e1000e_commit_phy(hw);

		mdelay(1);

		/* Force Full Duplex */

		e1e_rphy(hw, PHY_REG(769, 16), &phy_reg);

		e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x000C);

		/* Set Link Up (in force link) */

		e1e_rphy(hw, PHY_REG(776, 16), &phy_reg);

		e1e_wphy(hw, PHY_REG(776, 16), phy_reg | 0x0040);

		/* Force Link */

		e1e_rphy(hw, PHY_REG(769, 16), &phy_reg);

		e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x0040);

		/* Set Early Link Enable */

		e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);

		e1e_wphy(hw, PHY_REG(769, 20), phy_reg | 0x0400);

		/* fall through */

	default:

		/* force 1000, set loopback */

		e1e_wphy(hw, PHY_CONTROL, 0x4140);
@@ -1224,8 +1242,7 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter) 
			     E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */

			     E1000_CTRL_FD);	 /* Force Duplex to FULL */



		if ((adapter->hw.mac.type == e1000_ich8lan) ||

		    (adapter->hw.mac.type == e1000_ich9lan))

		if (adapter->flags & FLAG_IS_ICH)

			ctrl_reg |= E1000_CTRL_SLU;	/* Set Link Up */

	}

drivers/net/e1000e/hw.h

+22 −0
Original line number Diff line number Diff line
@@ -216,6 +216,21 @@ enum e1e_registers { 
#define IGP01E1000_PHY_LINK_HEALTH	0x13 /* PHY Link Health */

#define IGP02E1000_PHY_POWER_MGMT	0x19 /* Power Management */

#define IGP01E1000_PHY_PAGE_SELECT	0x1F /* Page Select */

#define BM_PHY_PAGE_SELECT		22   /* Page Select for BM */

#define IGP_PAGE_SHIFT			5

#define PHY_REG_MASK			0x1F



#define BM_WUC_PAGE			800

#define BM_WUC_ADDRESS_OPCODE		0x11

#define BM_WUC_DATA_OPCODE		0x12

#define BM_WUC_ENABLE_PAGE		769

#define BM_WUC_ENABLE_REG		17

#define BM_WUC_ENABLE_BIT		(1 << 2)

#define BM_WUC_HOST_WU_BIT		(1 << 4)



#define BM_WUC	PHY_REG(BM_WUC_PAGE, 1)

#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)

#define BM_WUS	PHY_REG(BM_WUC_PAGE, 3)



#define IGP01E1000_PHY_PCS_INIT_REG	0x00B4

#define IGP01E1000_PHY_POLARITY_MASK	0x0078
@@ -331,10 +346,16 @@ enum e1e_registers { 
#define E1000_DEV_ID_ICH8_IFE_G			0x10C5

#define E1000_DEV_ID_ICH8_IGP_M			0x104D

#define E1000_DEV_ID_ICH9_IGP_AMT		0x10BD

#define E1000_DEV_ID_ICH9_IGP_M_AMT		0x10F5

#define E1000_DEV_ID_ICH9_IGP_M			0x10BF

#define E1000_DEV_ID_ICH9_IGP_M_V		0x10CB

#define E1000_DEV_ID_ICH9_IGP_C			0x294C

#define E1000_DEV_ID_ICH9_IFE			0x10C0

#define E1000_DEV_ID_ICH9_IFE_GT		0x10C3

#define E1000_DEV_ID_ICH9_IFE_G			0x10C2

#define E1000_DEV_ID_ICH10_R_BM_LM		0x10CC

#define E1000_DEV_ID_ICH10_R_BM_LF		0x10CD

#define E1000_DEV_ID_ICH10_R_BM_V		0x10CE



#define E1000_FUNC_1 1
@@ -378,6 +399,7 @@ enum e1000_phy_type { 
	e1000_phy_gg82563,

	e1000_phy_igp_3,

	e1000_phy_ife,

	e1000_phy_bm,

};



enum e1000_bus_width {

drivers/net/e1000e/ich8lan.c

+82 −1
Original line number Diff line number Diff line
@@ -38,6 +38,12 @@ 
 * 82566DM Gigabit Network Connection

 * 82566MC Gigabit Network Connection

 * 82566MM Gigabit Network Connection

 * 82567LM Gigabit Network Connection

 * 82567LF Gigabit Network Connection

 * 82567LM-2 Gigabit Network Connection

 * 82567LF-2 Gigabit Network Connection

 * 82567V-2 Gigabit Network Connection

 * 82562GT-3 10/100 Network Connection

 */



#include <linux/netdevice.h>
@@ -198,6 +204,19 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 
	phy->addr			= 1;

	phy->reset_delay_us		= 100;



	/*

	 * We may need to do this twice - once for IGP and if that fails,

	 * we'll set BM func pointers and try again

	 */

	ret_val = e1000e_determine_phy_address(hw);

	if (ret_val) {

		hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;

		hw->phy.ops.read_phy_reg  = e1000e_read_phy_reg_bm;

		ret_val = e1000e_determine_phy_address(hw);

		if (ret_val)

			return ret_val;

	}



	phy->id = 0;

	while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&

	       (i++ < 100)) {
@@ -219,6 +238,13 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 
		phy->type = e1000_phy_ife;

		phy->autoneg_mask = E1000_ALL_NOT_GIG;

		break;

	case BME1000_E_PHY_ID:

		phy->type = e1000_phy_bm;

		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

		hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;

		hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;

		hw->phy.ops.commit_phy = e1000e_phy_sw_reset;

		break;

	default:

		return -E1000_ERR_PHY;

		break;
@@ -664,6 +690,7 @@ static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw) 
		return e1000_get_phy_info_ife_ich8lan(hw);

		break;

	case e1000_phy_igp_3:

	case e1000_phy_bm:

		return e1000e_get_phy_info_igp(hw);

		break;

	default:
@@ -728,7 +755,7 @@ static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 
	s32 ret_val = 0;

	u16 data;



	if (phy->type != e1000_phy_igp_3)

	if (phy->type == e1000_phy_ife)

		return ret_val;



	phy_ctrl = er32(PHY_CTRL);
@@ -1918,8 +1945,35 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 
		ret_val = e1000e_copper_link_setup_igp(hw);

		if (ret_val)

			return ret_val;

	} else if (hw->phy.type == e1000_phy_bm) {

		ret_val = e1000e_copper_link_setup_m88(hw);

		if (ret_val)

			return ret_val;

	}



	if (hw->phy.type == e1000_phy_ife) {

		ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);

		if (ret_val)

			return ret_val;



		reg_data &= ~IFE_PMC_AUTO_MDIX;



		switch (hw->phy.mdix) {

		case 1:

			reg_data &= ~IFE_PMC_FORCE_MDIX;

			break;

		case 2:

			reg_data |= IFE_PMC_FORCE_MDIX;

			break;

		case 0:

		default:

			reg_data |= IFE_PMC_AUTO_MDIX;

			break;

		}

		ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);

		if (ret_val)

			return ret_val;

	}

	return e1000e_setup_copper_link(hw);

}
@@ -2126,6 +2180,31 @@ void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 
				       reg_data);

}



/**

 *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL

 *  @hw: pointer to the HW structure

 *

 *  During S0 to Sx transition, it is possible the link remains at gig

 *  instead of negotiating to a lower speed.  Before going to Sx, set

 *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation

 *  to a lower speed.

 *

 *  Should only be called for ICH9 devices.

 **/

void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)

{

	u32 phy_ctrl;



	if (hw->mac.type == e1000_ich9lan) {

		phy_ctrl = er32(PHY_CTRL);

		phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |

		            E1000_PHY_CTRL_GBE_DISABLE;

		ew32(PHY_CTRL, phy_ctrl);

	}



	return;

}



/**

 *  e1000_cleanup_led_ich8lan - Restore the default LED operation

 *  @hw: pointer to the HW structure
@@ -2247,6 +2326,7 @@ static struct e1000_nvm_operations ich8_nvm_ops = { 
struct e1000_info e1000_ich8_info = {

	.mac			= e1000_ich8lan,

	.flags			= FLAG_HAS_WOL

				  | FLAG_IS_ICH

				  | FLAG_RX_CSUM_ENABLED

				  | FLAG_HAS_CTRLEXT_ON_LOAD

				  | FLAG_HAS_AMT
@@ -2262,6 +2342,7 @@ struct e1000_info e1000_ich8_info = { 
struct e1000_info e1000_ich9_info = {

	.mac			= e1000_ich9lan,

	.flags			= FLAG_HAS_JUMBO_FRAMES

				  | FLAG_IS_ICH

				  | FLAG_HAS_WOL

				  | FLAG_RX_CSUM_ENABLED

				  | FLAG_HAS_CTRLEXT_ON_LOAD