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Commit 974a3abc authored by Stefan Agner's avatar Stefan Agner Committed by Shawn Guo
Browse files

ARM: dts: imx7d: move ARM platform peripherals inside soc node 



Since we have a SoC level node we should make use of it and have
all nodes which are within the SoC, inside that node. This also
saves an extra interrupt-parent properties. While at it, also
order the Coresight nodes according to register addresses.

Signed-off-by: default avatarStefan Agner <stefan@agner.ch>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 2a8e583c

arch/arm/boot/dts/imx7d.dtsi

+17 −15
Original line number Original line Diff line number Diff line
@@ -52,6 +52,7 @@ 
		};

		};

	};

	};





	soc {

		etm@3007d000 {

		etm@3007d000 {

			compatible = "arm,coresight-etm3x", "arm,primecell";

			compatible = "arm,coresight-etm3x", "arm,primecell";

			reg = <0x3007d000 0x1000>;

			reg = <0x3007d000 0x1000>;
@@ -73,6 +74,7 @@ 
			};

			};

		};

		};

	};

	};

};





&aips3 {

&aips3 {

	usbotg2: usb@30b20000 {

	usbotg2: usb@30b20000 {

arch/arm/boot/dts/imx7s.dtsi

+150 −151
Original line number Original line Diff line number Diff line
@@ -95,16 +95,6 @@ 
		};

		};

	};

	};





	intc: interrupt-controller@31001000 {

		compatible = "arm,cortex-a7-gic";

		#interrupt-cells = <3>;

		interrupt-controller;

		reg = <0x31001000 0x1000>,

		      <0x31002000 0x1000>,

		      <0x31004000 0x2000>,

		      <0x31006000 0x2000>;

	};



	ckil: clock-cki {

	ckil: clock-cki {

		compatible = "fixed-clock";

		compatible = "fixed-clock";

		#clock-cells = <0>;

		#clock-cells = <0>;
@@ -119,77 +109,92 @@ 
		clock-output-names = "osc";

		clock-output-names = "osc";

	};

	};





	timer {

	soc {

		compatible = "arm,armv7-timer";

		#address-cells = <1>;

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

		#size-cells = <1>;

			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

		compatible = "simple-bus";

			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

		interrupt-parent = <&intc>;

		interrupt-parent = <&intc>;

	};

		ranges;





	etr@30086000 {

		funnel@30041000 {

		compatible = "arm,coresight-tmc", "arm,primecell";

			compatible = "arm,coresight-funnel", "arm,primecell";

		reg = <0x30086000 0x1000>;

			reg = <0x30041000 0x1000>;

			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;

			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;

			clock-names = "apb_pclk";

			clock-names = "apb_pclk";





		port {

			ca_funnel_ports: ports {

			etr_in_port: endpoint {

				#address-cells = <1>;

				#size-cells = <0>;



				/* funnel input ports */

				port@0 {

					reg = <0>;

					ca_funnel_in_port0: endpoint {

						slave-mode;

						slave-mode;

				remote-endpoint = <&replicator_out_port1>;

						remote-endpoint = <&etm0_out_port>;

					};

				};

				};



				/* funnel output port */

				port@2 {

					reg = <0>;

					ca_funnel_out_port0: endpoint {

						remote-endpoint = <&hugo_funnel_in_port0>;

					};

					};

				};

				};





	tpiu@30087000 {

				/* the other input ports are not connect to anything */

		compatible = "arm,coresight-tpiu", "arm,primecell";

			};

		reg = <0x30087000 0x1000>;

		};



		etm@3007c000 {

			compatible = "arm,coresight-etm3x", "arm,primecell";

			reg = <0x3007c000 0x1000>;

			cpu = <&cpu0>;

			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;

			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;

			clock-names = "apb_pclk";

			clock-names = "apb_pclk";





			port {

			port {

			tpiu_in_port: endpoint {

				etm0_out_port: endpoint {

				slave-mode;

					remote-endpoint = <&ca_funnel_in_port0>;

				remote-endpoint = <&replicator_out_port1>;

				};

				};

			};

			};

		};

		};





	replicator {

		funnel@30083000 {

		/*

			compatible = "arm,coresight-funnel", "arm,primecell";

		 * non-configurable replicators don't show up on the

			reg = <0x30083000 0x1000>;

		 * AMBA bus.  As such no need to add "arm,primecell"

			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;

		 */

			clock-names = "apb_pclk";

		compatible = "arm,coresight-replicator";





			ports {

			ports {

				#address-cells = <1>;

				#address-cells = <1>;

				#size-cells = <0>;

				#size-cells = <0>;





			/* replicator output ports */

				/* funnel input ports */

				port@0 {

				port@0 {

					reg = <0>;

					reg = <0>;

				replicator_out_port0: endpoint {

					hugo_funnel_in_port0: endpoint {

					remote-endpoint = <&tpiu_in_port>;

						slave-mode;

						remote-endpoint = <&ca_funnel_out_port0>;

					};

					};

				};

				};





				port@1 {

				port@1 {

					reg = <1>;

					reg = <1>;

				replicator_out_port1: endpoint {

					hugo_funnel_in_port1: endpoint {

					remote-endpoint = <&etr_in_port>;

						slave-mode; /* M4 input */

					};

					};

				};

				};





			/* replicator input port */

				port@2 {

				port@2 {

					reg = <0>;

					reg = <0>;

				replicator_in_port0: endpoint {

					hugo_funnel_out_port0: endpoint {

					slave-mode;

						remote-endpoint = <&etf_in_port>;

					remote-endpoint = <&etf_out_port>;

					};

					};

				};

				};



				/* the other input ports are not connect to anything */

			};

			};

		};

		};
@@ -220,94 +225,88 @@ 
			};

			};

		};

		};





	funnel@30083000 {

		etr@30086000 {

		compatible = "arm,coresight-funnel", "arm,primecell";

			compatible = "arm,coresight-tmc", "arm,primecell";

		reg = <0x30083000 0x1000>;

			reg = <0x30086000 0x1000>;

			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;

			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;

			clock-names = "apb_pclk";

			clock-names = "apb_pclk";





		ports {

			port {

			#address-cells = <1>;

				etr_in_port: endpoint {

			#size-cells = <0>;



			/* funnel input ports */

			port@0 {

				reg = <0>;

				hugo_funnel_in_port0: endpoint {

					slave-mode;

					slave-mode;

					remote-endpoint = <&ca_funnel_out_port0>;

					remote-endpoint = <&replicator_out_port1>;

				};

				};

				};



			port@1 {

				reg = <1>;

				hugo_funnel_in_port1: endpoint {

					slave-mode; /* M4 input */

			};

			};

		};

		};





			port@2 {

		tpiu@30087000 {

				reg = <0>;

			compatible = "arm,coresight-tpiu", "arm,primecell";

				hugo_funnel_out_port0: endpoint {

			reg = <0x30087000 0x1000>;

					remote-endpoint = <&etf_in_port>;

			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;

				};

			clock-names = "apb_pclk";

			};





			/* the other input ports are not connect to anything */

			port {

				tpiu_in_port: endpoint {

					slave-mode;

					remote-endpoint = <&replicator_out_port1>;

				};

			};

			};

		};

		};





	funnel@30041000 {

		replicator {

		compatible = "arm,coresight-funnel", "arm,primecell";

			/*

		reg = <0x30041000 0x1000>;

			 * non-configurable replicators don't show up on the

		clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;

			 * AMBA bus.  As such no need to add "arm,primecell"

		clock-names = "apb_pclk";

			 */

			compatible = "arm,coresight-replicator";





		ca_funnel_ports: ports {

			ports {

				#address-cells = <1>;

				#address-cells = <1>;

				#size-cells = <0>;

				#size-cells = <0>;





			/* funnel input ports */

				/* replicator output ports */

				port@0 {

				port@0 {

					reg = <0>;

					reg = <0>;

				ca_funnel_in_port0: endpoint {

					replicator_out_port0: endpoint {

					slave-mode;

						remote-endpoint = <&tpiu_in_port>;

					remote-endpoint = <&etm0_out_port>;

					};

					};

				};

				};





			/* funnel output port */

				port@1 {

			port@2 {

					reg = <1>;

				reg = <0>;

					replicator_out_port1: endpoint {

				ca_funnel_out_port0: endpoint {

						remote-endpoint = <&etr_in_port>;

					remote-endpoint = <&hugo_funnel_in_port0>;

					};

					};

				};

				};





			/* the other input ports are not connect to anything */

				/* replicator input port */

				port@2 {

					reg = <0>;

					replicator_in_port0: endpoint {

						slave-mode;

						remote-endpoint = <&etf_out_port>;

					};

					};

				};

				};



	etm@3007c000 {

		compatible = "arm,coresight-etm3x", "arm,primecell";

		reg = <0x3007c000 0x1000>;

		cpu = <&cpu0>;

		clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;

		clock-names = "apb_pclk";



		port {

			etm0_out_port: endpoint {

				remote-endpoint = <&ca_funnel_in_port0>;

			};

			};

		};

		};



		intc: interrupt-controller@31001000 {

			compatible = "arm,cortex-a7-gic";

			#interrupt-cells = <3>;

			interrupt-controller;

			reg = <0x31001000 0x1000>,

			      <0x31002000 0x1000>,

			      <0x31004000 0x2000>,

			      <0x31006000 0x2000>;

		};

		};





	soc {

		timer {

		#address-cells = <1>;

			compatible = "arm,armv7-timer";

		#size-cells = <1>;

			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

		compatible = "simple-bus";

				     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

		interrupt-parent = <&intc>;

				     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

		ranges;

				     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

		};





		aips1: aips-bus@30000000 {

		aips1: aips-bus@30000000 {

			compatible = "fsl,aips-bus", "simple-bus";

			compatible = "fsl,aips-bus", "simple-bus";