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Commit 97114f39 authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'imx-clk-common-fixes' of git://git.pengutronix.de/git/imx/linux-2.6 into fixes

From Sascha Hauer: "Some fixes for the fresh i.MX common clock support"

Resolved trivial conflict in arch/arm/plat-mxc/include/mach/common.h.

* tag 'imx-clk-common-fixes' of git://git.pengutronix.de/git/imx/linux-2.6

:
  ARM: imx6q: prepare and enable init on clks directly instead of clk_get first
  ARM i.MX: remove now unnecessary argument from mxc_timer_init
  ARM: i.MX: change timer clock from ipg to perclk
  ARM i.MX5: fix gpt peripheral clock path

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents f8f5701b b0286f20
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+1 −2
Original line number Diff line number Diff line
@@ -108,8 +108,7 @@ int __init mx1_clocks_init(unsigned long fref)
	clk_register_clkdev(clk[clk32], NULL, "mxc_rtc.0");
	clk_register_clkdev(clk[clko], "clko", NULL);

	mxc_timer_init(NULL, MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR),
			MX1_TIM1_INT);
	mxc_timer_init(MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), MX1_TIM1_INT);

	return 0;
}
+2 −2
Original line number Diff line number Diff line
@@ -180,7 +180,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
	clk_register_clkdev(clk[sdhc1_ipg_gate], "sdhc1", NULL);
	clk_register_clkdev(clk[sdhc2_ipg_gate], "sdhc2", NULL);

	mxc_timer_init(NULL, MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR),
			MX21_INT_GPT1);
	mxc_timer_init(MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), MX21_INT_GPT1);

	return 0;
}
+1 −1
Original line number Diff line number Diff line
@@ -243,6 +243,6 @@ int __init mx25_clocks_init(void)
	clk_register_clkdev(clk[sdma_ahb], "ahb", "imx35-sdma");
	clk_register_clkdev(clk[iim_ipg], "iim", NULL);

	mxc_timer_init(NULL, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
	mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
	return 0;
}
+1 −2
Original line number Diff line number Diff line
@@ -263,8 +263,7 @@ int __init mx27_clocks_init(unsigned long fref)
	clk_register_clkdev(clk[ssi1_baud_gate], "bitrate" , "imx-ssi.0");
	clk_register_clkdev(clk[ssi2_baud_gate], "bitrate" , "imx-ssi.1");

	mxc_timer_init(NULL, MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR),
			MX27_INT_GPT1);
	mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);

	clk_prepare_enable(clk[emi_ahb_gate]);

+1 −2
Original line number Diff line number Diff line
@@ -175,8 +175,7 @@ int __init mx31_clocks_init(unsigned long fref)
	mx31_revision();
	clk_disable_unprepare(clk[iim_gate]);

	mxc_timer_init(NULL, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR),
			MX31_INT_GPT);
	mxc_timer_init(MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR), MX31_INT_GPT);

	return 0;
}
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