Loading arch/arm/mach-omap2/board-overo.c +1 −0 Original line number Diff line number Diff line Loading @@ -52,6 +52,7 @@ #define OVERO_GPIO_BT_XGATE 15 #define OVERO_GPIO_W2W_NRESET 16 #define OVERO_GPIO_PENDOWN 114 #define OVERO_GPIO_BT_NRESET 164 #define OVERO_GPIO_USBH_CPEN 168 #define OVERO_GPIO_USBH_NRESET 183 Loading arch/arm/mach-omap2/cm.h +3 −3 Original line number Diff line number Diff line Loading @@ -29,9 +29,9 @@ * These registers appear once per CM module. */ #define OMAP3430_CM_REVISION OMAP_CM_REGADDR(OCP_MOD, 0x0000) #define OMAP3430_CM_SYSCONFIG OMAP_CM_REGADDR(OCP_MOD, 0x0010) #define OMAP3430_CM_POLCTRL OMAP_CM_REGADDR(OCP_MOD, 0x009c) #define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000) #define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010) #define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c) #define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070 #define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) Loading arch/arm/mach-omap2/pm.h +0 −3 Original line number Diff line number Diff line Loading @@ -11,9 +11,6 @@ #ifndef __ARCH_ARM_MACH_OMAP2_PM_H #define __ARCH_ARM_MACH_OMAP2_PM_H extern int omap2_pm_init(void); extern int omap3_pm_init(void); #ifdef CONFIG_PM_DEBUG extern void omap2_pm_dump(int mode, int resume, unsigned int us); extern int omap2_pm_debug; Loading arch/arm/mach-omap2/pm24xx.c +1 −1 Original line number Diff line number Diff line Loading @@ -470,7 +470,7 @@ static void __init prcm_setup_regs(void) WKUP_MOD, PM_WKEN); } int __init omap2_pm_init(void) static int __init omap2_pm_init(void) { u32 l; Loading arch/arm/mach-omap2/pm34xx.c +47 −4 Original line number Diff line number Diff line Loading @@ -39,7 +39,9 @@ struct power_state { struct powerdomain *pwrdm; u32 next_state; #ifdef CONFIG_SUSPEND u32 saved_state; #endif struct list_head node; }; Loading Loading @@ -293,6 +295,9 @@ static void omap3_pm_idle(void) local_irq_enable(); } #ifdef CONFIG_SUSPEND static suspend_state_t suspend_state; static int omap3_pm_prepare(void) { disable_hlt(); Loading Loading @@ -321,7 +326,6 @@ static int omap3_pm_suspend(void) restore: /* Restore next_pwrsts */ list_for_each_entry(pwrst, &pwrst_list, node) { set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); state = pwrdm_read_prev_pwrst(pwrst->pwrdm); if (state > pwrst->next_state) { printk(KERN_INFO "Powerdomain (%s) didn't enter " Loading @@ -329,6 +333,7 @@ static int omap3_pm_suspend(void) pwrst->pwrdm->name, pwrst->next_state); ret = -1; } set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); } if (ret) printk(KERN_ERR "Could not enter target state in pm_suspend\n"); Loading @@ -339,11 +344,11 @@ static int omap3_pm_suspend(void) return ret; } static int omap3_pm_enter(suspend_state_t state) static int omap3_pm_enter(suspend_state_t unused) { int ret = 0; switch (state) { switch (suspend_state) { case PM_SUSPEND_STANDBY: case PM_SUSPEND_MEM: ret = omap3_pm_suspend(); Loading @@ -360,12 +365,30 @@ static void omap3_pm_finish(void) enable_hlt(); } /* Hooks to enable / disable UART interrupts during suspend */ static int omap3_pm_begin(suspend_state_t state) { suspend_state = state; omap_uart_enable_irqs(0); return 0; } static void omap3_pm_end(void) { suspend_state = PM_SUSPEND_ON; omap_uart_enable_irqs(1); return; } static struct platform_suspend_ops omap_pm_ops = { .begin = omap3_pm_begin, .end = omap3_pm_end, .prepare = omap3_pm_prepare, .enter = omap3_pm_enter, .finish = omap3_pm_finish, .valid = suspend_valid_only_mem, }; #endif /* CONFIG_SUSPEND */ /** Loading Loading @@ -613,6 +636,24 @@ static void __init prcm_setup_regs(void) /* Clear any pending PRCM interrupts */ prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); /* Don't attach IVA interrupts */ prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); /* Clear any pending 'reset' flags */ prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST); prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST); prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST); prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST); prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST); prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST); prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST); /* Clear any pending PRCM interrupts */ prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); omap3_iva_idle(); omap3_d2d_idle(); } Loading Loading @@ -652,7 +693,7 @@ static int __init clkdms_setup(struct clockdomain *clkdm) return 0; } int __init omap3_pm_init(void) static int __init omap3_pm_init(void) { struct power_state *pwrst, *tmp; int ret; Loading Loading @@ -692,7 +733,9 @@ int __init omap3_pm_init(void) _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, omap34xx_cpu_suspend_sz); #ifdef CONFIG_SUSPEND suspend_set_ops(&omap_pm_ops); #endif /* CONFIG_SUSPEND */ pm_idle = omap3_pm_idle; Loading Loading
arch/arm/mach-omap2/board-overo.c +1 −0 Original line number Diff line number Diff line Loading @@ -52,6 +52,7 @@ #define OVERO_GPIO_BT_XGATE 15 #define OVERO_GPIO_W2W_NRESET 16 #define OVERO_GPIO_PENDOWN 114 #define OVERO_GPIO_BT_NRESET 164 #define OVERO_GPIO_USBH_CPEN 168 #define OVERO_GPIO_USBH_NRESET 183 Loading
arch/arm/mach-omap2/cm.h +3 −3 Original line number Diff line number Diff line Loading @@ -29,9 +29,9 @@ * These registers appear once per CM module. */ #define OMAP3430_CM_REVISION OMAP_CM_REGADDR(OCP_MOD, 0x0000) #define OMAP3430_CM_SYSCONFIG OMAP_CM_REGADDR(OCP_MOD, 0x0010) #define OMAP3430_CM_POLCTRL OMAP_CM_REGADDR(OCP_MOD, 0x009c) #define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000) #define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010) #define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c) #define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070 #define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) Loading
arch/arm/mach-omap2/pm.h +0 −3 Original line number Diff line number Diff line Loading @@ -11,9 +11,6 @@ #ifndef __ARCH_ARM_MACH_OMAP2_PM_H #define __ARCH_ARM_MACH_OMAP2_PM_H extern int omap2_pm_init(void); extern int omap3_pm_init(void); #ifdef CONFIG_PM_DEBUG extern void omap2_pm_dump(int mode, int resume, unsigned int us); extern int omap2_pm_debug; Loading
arch/arm/mach-omap2/pm24xx.c +1 −1 Original line number Diff line number Diff line Loading @@ -470,7 +470,7 @@ static void __init prcm_setup_regs(void) WKUP_MOD, PM_WKEN); } int __init omap2_pm_init(void) static int __init omap2_pm_init(void) { u32 l; Loading
arch/arm/mach-omap2/pm34xx.c +47 −4 Original line number Diff line number Diff line Loading @@ -39,7 +39,9 @@ struct power_state { struct powerdomain *pwrdm; u32 next_state; #ifdef CONFIG_SUSPEND u32 saved_state; #endif struct list_head node; }; Loading Loading @@ -293,6 +295,9 @@ static void omap3_pm_idle(void) local_irq_enable(); } #ifdef CONFIG_SUSPEND static suspend_state_t suspend_state; static int omap3_pm_prepare(void) { disable_hlt(); Loading Loading @@ -321,7 +326,6 @@ static int omap3_pm_suspend(void) restore: /* Restore next_pwrsts */ list_for_each_entry(pwrst, &pwrst_list, node) { set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); state = pwrdm_read_prev_pwrst(pwrst->pwrdm); if (state > pwrst->next_state) { printk(KERN_INFO "Powerdomain (%s) didn't enter " Loading @@ -329,6 +333,7 @@ static int omap3_pm_suspend(void) pwrst->pwrdm->name, pwrst->next_state); ret = -1; } set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); } if (ret) printk(KERN_ERR "Could not enter target state in pm_suspend\n"); Loading @@ -339,11 +344,11 @@ static int omap3_pm_suspend(void) return ret; } static int omap3_pm_enter(suspend_state_t state) static int omap3_pm_enter(suspend_state_t unused) { int ret = 0; switch (state) { switch (suspend_state) { case PM_SUSPEND_STANDBY: case PM_SUSPEND_MEM: ret = omap3_pm_suspend(); Loading @@ -360,12 +365,30 @@ static void omap3_pm_finish(void) enable_hlt(); } /* Hooks to enable / disable UART interrupts during suspend */ static int omap3_pm_begin(suspend_state_t state) { suspend_state = state; omap_uart_enable_irqs(0); return 0; } static void omap3_pm_end(void) { suspend_state = PM_SUSPEND_ON; omap_uart_enable_irqs(1); return; } static struct platform_suspend_ops omap_pm_ops = { .begin = omap3_pm_begin, .end = omap3_pm_end, .prepare = omap3_pm_prepare, .enter = omap3_pm_enter, .finish = omap3_pm_finish, .valid = suspend_valid_only_mem, }; #endif /* CONFIG_SUSPEND */ /** Loading Loading @@ -613,6 +636,24 @@ static void __init prcm_setup_regs(void) /* Clear any pending PRCM interrupts */ prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); /* Don't attach IVA interrupts */ prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); /* Clear any pending 'reset' flags */ prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST); prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST); prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST); prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST); prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST); prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST); prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST); /* Clear any pending PRCM interrupts */ prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); omap3_iva_idle(); omap3_d2d_idle(); } Loading Loading @@ -652,7 +693,7 @@ static int __init clkdms_setup(struct clockdomain *clkdm) return 0; } int __init omap3_pm_init(void) static int __init omap3_pm_init(void) { struct power_state *pwrst, *tmp; int ret; Loading Loading @@ -692,7 +733,9 @@ int __init omap3_pm_init(void) _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, omap34xx_cpu_suspend_sz); #ifdef CONFIG_SUSPEND suspend_set_ops(&omap_pm_ops); #endif /* CONFIG_SUSPEND */ pm_idle = omap3_pm_idle; Loading