UAPI: (Scripted) Disintegrate arch/alpha/include/asm (96433f6e) · Commits · e / devices / android_kernel_teracube_2e

arch/alpha/include/asm/Kbuild

+0 −9

Original line number	Diff line number	Diff line
		include include/asm-generic/Kbuild.asm

		generic-y += clkdev.h

		header-y += compiler.h
		header-y += console.h
		header-y += fpu.h
		header-y += gentrap.h
		header-y += pal.h
		header-y += reg.h
		header-y += regdef.h
		header-y += sysinfo.h
		generic-y += exec.h
		generic-y += trace_clock.h

arch/alpha/include/asm/a.out.h

+1 −88

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		#ifndef __ALPHA_A_OUT_H__
		#define __ALPHA_A_OUT_H__

		#include <linux/types.h>
		#include <uapi/asm/a.out.h>

		/*
		* OSF/1 ECOFF header structs. ECOFF files consist of:
		* - a file header (struct filehdr),
		* - an a.out header (struct aouthdr),
		* - one or more section headers (struct scnhdr).
		* The filhdr's "f_nscns" field contains the
		* number of section headers.
		*/

		struct filehdr
		{
		/* OSF/1 "file" header */
		__u16 f_magic, f_nscns;
		__u32 f_timdat;
		__u64 f_symptr;
		__u32 f_nsyms;
		__u16 f_opthdr, f_flags;
		};

		struct aouthdr
		{
		__u64 info; /* after that it looks quite normal.. */
		__u64 tsize;
		__u64 dsize;
		__u64 bsize;
		__u64 entry;
		__u64 text_start; /* with a few additions that actually make sense */
		__u64 data_start;
		__u64 bss_start;
		__u32 gprmask, fprmask; /* bitmask of general & floating point regs used in binary */
		__u64 gpvalue;
		};

		struct scnhdr
		{
		char s_name[8];
		__u64 s_paddr;
		__u64 s_vaddr;
		__u64 s_size;
		__u64 s_scnptr;
		__u64 s_relptr;
		__u64 s_lnnoptr;
		__u16 s_nreloc;
		__u16 s_nlnno;
		__u32 s_flags;
		};

		struct exec
		{
		/* OSF/1 "file" header */
		struct filehdr fh;
		struct aouthdr ah;
		};

		/*
		* Define's so that the kernel exec code can access the a.out header
		* fields...
		*/
		#define a_info ah.info
		#define a_text ah.tsize
		#define a_data ah.dsize
		#define a_bss ah.bsize
		#define a_entry ah.entry
		#define a_textstart ah.text_start
		#define a_datastart ah.data_start
		#define a_bssstart ah.bss_start
		#define a_gprmask ah.gprmask
		#define a_fprmask ah.fprmask
		#define a_gpvalue ah.gpvalue

		#define N_TXTADDR(x) ((x).a_textstart)
		#define N_DATADDR(x) ((x).a_datastart)
		#define N_BSSADDR(x) ((x).a_bssstart)
		#define N_DRSIZE(x) 0
		#define N_TRSIZE(x) 0
		#define N_SYMSIZE(x) 0

		#define AOUTHSZ sizeof(struct aouthdr)
		#define SCNHSZ sizeof(struct scnhdr)
		#define SCNROUND 16

		#define N_TXTOFF(x) \
		((long) N_MAGIC(x) == ZMAGIC ? 0 : \
		(sizeof(struct exec) + (x).fh.f_nscns*SCNHSZ + SCNROUND - 1) & ~(SCNROUND - 1))

		#ifdef __KERNEL__

		/* Assume that start addresses below 4G belong to a TASO application.
		Unfortunately, there is no proper bit in the exec header to check.
		@@ -98,5 +12,4 @@ struct exec
		set_personality (((BFPM->taso \|\| EX.ah.entry < 0x100000000L \
		? ADDR_LIMIT_32BIT : 0) \| PER_OSF4))

		#endif /* __KERNEL__ */
		#endif /* __A_OUT_GNU_H__ */

arch/alpha/include/asm/compiler.h

+1 −114

Original line number	Diff line number	Diff line
		#ifndef __ALPHA_COMPILER_H
		#define __ALPHA_COMPILER_H

		/*
		* Herein are macros we use when describing various patterns we want to GCC.
		* In all cases we can get better schedules out of the compiler if we hide
		* as little as possible inside inline assembly. However, we want to be
		* able to know what we'll get out before giving up inline assembly. Thus
		* these tests and macros.
		*/
		#include <uapi/asm/compiler.h>

		#if __GNUC__ == 3 && __GNUC_MINOR__ >= 4 \|\| __GNUC__ > 3
		# define __kernel_insbl(val, shift) __builtin_alpha_insbl(val, shift)
		# define __kernel_inswl(val, shift) __builtin_alpha_inswl(val, shift)
		# define __kernel_insql(val, shift) __builtin_alpha_insql(val, shift)
		# define __kernel_inslh(val, shift) __builtin_alpha_inslh(val, shift)
		# define __kernel_extbl(val, shift) __builtin_alpha_extbl(val, shift)
		# define __kernel_extwl(val, shift) __builtin_alpha_extwl(val, shift)
		# define __kernel_cmpbge(a, b) __builtin_alpha_cmpbge(a, b)
		#else
		# define __kernel_insbl(val, shift) \
		({ unsigned long __kir; \
		__asm__("insbl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \
		__kir; })
		# define __kernel_inswl(val, shift) \
		({ unsigned long __kir; \
		__asm__("inswl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \
		__kir; })
		# define __kernel_insql(val, shift) \
		({ unsigned long __kir; \
		__asm__("insql %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \
		__kir; })
		# define __kernel_inslh(val, shift) \
		({ unsigned long __kir; \
		__asm__("inslh %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \
		__kir; })
		# define __kernel_extbl(val, shift) \
		({ unsigned long __kir; \
		__asm__("extbl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \
		__kir; })
		# define __kernel_extwl(val, shift) \
		({ unsigned long __kir; \
		__asm__("extwl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \
		__kir; })
		# define __kernel_cmpbge(a, b) \
		({ unsigned long __kir; \
		__asm__("cmpbge %r2,%1,%0" : "=r"(__kir) : "rI"(b), "rJ"(a)); \
		__kir; })
		#endif

		#ifdef __alpha_cix__
		# if __GNUC__ == 3 && __GNUC_MINOR__ >= 4 \|\| __GNUC__ > 3
		# define __kernel_cttz(x) __builtin_ctzl(x)
		# define __kernel_ctlz(x) __builtin_clzl(x)
		# define __kernel_ctpop(x) __builtin_popcountl(x)
		# else
		# define __kernel_cttz(x) \
		({ unsigned long __kir; \
		__asm__("cttz %1,%0" : "=r"(__kir) : "r"(x)); \
		__kir; })
		# define __kernel_ctlz(x) \
		({ unsigned long __kir; \
		__asm__("ctlz %1,%0" : "=r"(__kir) : "r"(x)); \
		__kir; })
		# define __kernel_ctpop(x) \
		({ unsigned long __kir; \
		__asm__("ctpop %1,%0" : "=r"(__kir) : "r"(x)); \
		__kir; })
		# endif
		#else
		# define __kernel_cttz(x) \
		({ unsigned long __kir; \
		__asm__(".arch ev67; cttz %1,%0" : "=r"(__kir) : "r"(x)); \
		__kir; })
		# define __kernel_ctlz(x) \
		({ unsigned long __kir; \
		__asm__(".arch ev67; ctlz %1,%0" : "=r"(__kir) : "r"(x)); \
		__kir; })
		# define __kernel_ctpop(x) \
		({ unsigned long __kir; \
		__asm__(".arch ev67; ctpop %1,%0" : "=r"(__kir) : "r"(x)); \
		__kir; })
		#endif


		/*
		* Beginning with EGCS 1.1, GCC defines __alpha_bwx__ when the BWX
		* extension is enabled. Previous versions did not define anything
		* we could test during compilation -- too bad, so sad.
		*/

		#if defined(__alpha_bwx__)
		#define __kernel_ldbu(mem) (mem)
		#define __kernel_ldwu(mem) (mem)
		#define __kernel_stb(val,mem) ((mem) = (val))
		#define __kernel_stw(val,mem) ((mem) = (val))
		#else
		#define __kernel_ldbu(mem) \
		({ unsigned char __kir; \
		__asm__(".arch ev56; \
		ldbu %0,%1" : "=r"(__kir) : "m"(mem)); \
		__kir; })
		#define __kernel_ldwu(mem) \
		({ unsigned short __kir; \
		__asm__(".arch ev56; \
		ldwu %0,%1" : "=r"(__kir) : "m"(mem)); \
		__kir; })
		#define __kernel_stb(val,mem) \
		__asm__(".arch ev56; \
		stb %1,%0" : "=m"(mem) : "r"(val))
		#define __kernel_stw(val,mem) \
		__asm__(".arch ev56; \
		stw %1,%0" : "=m"(mem) : "r"(val))
		#endif

		#ifdef __KERNEL__
		/* Some idiots over in <linux/compiler.h> thought inline should imply
		always_inline. This breaks stuff. We'll include this file whenever
		we run into such problems. */
		@@ -125,6 +14,4 @@
		#undef __always_inline
		#define __always_inline inline __attribute__((always_inline))

		#endif /* __KERNEL__ */

		#endif /* __ALPHA_COMPILER_H */

arch/alpha/include/asm/console.h

+1 −47

Original line number	Diff line number	Diff line
		#ifndef __AXP_CONSOLE_H
		#define __AXP_CONSOLE_H

		/*
		* Console callback routine numbers
		*/
		#define CCB_GETC 0x01
		#define CCB_PUTS 0x02
		#define CCB_RESET_TERM 0x03
		#define CCB_SET_TERM_INT 0x04
		#define CCB_SET_TERM_CTL 0x05
		#define CCB_PROCESS_KEYCODE 0x06
		#define CCB_OPEN_CONSOLE 0x07
		#define CCB_CLOSE_CONSOLE 0x08
		#include <uapi/asm/console.h>

		#define CCB_OPEN 0x10
		#define CCB_CLOSE 0x11
		#define CCB_IOCTL 0x12
		#define CCB_READ 0x13
		#define CCB_WRITE 0x14

		#define CCB_SET_ENV 0x20
		#define CCB_RESET_ENV 0x21
		#define CCB_GET_ENV 0x22
		#define CCB_SAVE_ENV 0x23

		#define CCB_PSWITCH 0x30
		#define CCB_BIOS_EMUL 0x32

		/*
		* Environment variable numbers
		*/
		#define ENV_AUTO_ACTION 0x01
		#define ENV_BOOT_DEV 0x02
		#define ENV_BOOTDEF_DEV 0x03
		#define ENV_BOOTED_DEV 0x04
		#define ENV_BOOT_FILE 0x05
		#define ENV_BOOTED_FILE 0x06
		#define ENV_BOOT_OSFLAGS 0x07
		#define ENV_BOOTED_OSFLAGS 0x08
		#define ENV_BOOT_RESET 0x09
		#define ENV_DUMP_DEV 0x0A
		#define ENV_ENABLE_AUDIT 0x0B
		#define ENV_LICENSE 0x0C
		#define ENV_CHAR_SET 0x0D
		#define ENV_LANGUAGE 0x0E
		#define ENV_TTY_DEV 0x0F

		#ifdef __KERNEL__
		#ifndef __ASSEMBLY__
		extern long callback_puts(long unit, const char *s, long length);
		extern long callback_getc(long unit);
		@@ -70,6 +26,4 @@ struct hwrpb_struct;
		extern int callback_init_done;
		extern void * callback_init(void *);
		#endif /* __ASSEMBLY__ */
		#endif /* __KERNEL__ */

		#endif /* __AXP_CONSOLE_H */

arch/alpha/include/asm/fpu.h

+1 −123

Original line number	Diff line number	Diff line
		#ifndef __ASM_ALPHA_FPU_H
		#define __ASM_ALPHA_FPU_H

		#ifdef __KERNEL__
		#include <asm/special_insns.h>
		#endif

		/*
		* Alpha floating-point control register defines:
		*/
		#define FPCR_DNOD (1UL<<47) /* denorm INV trap disable */
		#define FPCR_DNZ (1UL<<48) /* denorms to zero */
		#define FPCR_INVD (1UL<<49) /* invalid op disable (opt.) */
		#define FPCR_DZED (1UL<<50) /* division by zero disable (opt.) */
		#define FPCR_OVFD (1UL<<51) /* overflow disable (optional) */
		#define FPCR_INV (1UL<<52) /* invalid operation */
		#define FPCR_DZE (1UL<<53) /* division by zero */
		#define FPCR_OVF (1UL<<54) /* overflow */
		#define FPCR_UNF (1UL<<55) /* underflow */
		#define FPCR_INE (1UL<<56) /* inexact */
		#define FPCR_IOV (1UL<<57) /* integer overflow */
		#define FPCR_UNDZ (1UL<<60) /* underflow to zero (opt.) */
		#define FPCR_UNFD (1UL<<61) /* underflow disable (opt.) */
		#define FPCR_INED (1UL<<62) /* inexact disable (opt.) */
		#define FPCR_SUM (1UL<<63) /* summary bit */

		#define FPCR_DYN_SHIFT 58 /* first dynamic rounding mode bit */
		#define FPCR_DYN_CHOPPED (0x0UL << FPCR_DYN_SHIFT) /* towards 0 */
		#define FPCR_DYN_MINUS (0x1UL << FPCR_DYN_SHIFT) /* towards -INF */
		#define FPCR_DYN_NORMAL (0x2UL << FPCR_DYN_SHIFT) /* towards nearest */
		#define FPCR_DYN_PLUS (0x3UL << FPCR_DYN_SHIFT) /* towards +INF */
		#define FPCR_DYN_MASK (0x3UL << FPCR_DYN_SHIFT)

		#define FPCR_MASK 0xffff800000000000L

		/*
		* IEEE trap enables are implemented in software. These per-thread
		* bits are stored in the "ieee_state" field of "struct thread_info".
		* Thus, the bits are defined so as not to conflict with the
		* floating-point enable bit (which is architected). On top of that,
		* we want to make these bits compatible with OSF/1 so
		* ieee_set_fp_control() etc. can be implemented easily and
		* compatibly. The corresponding definitions are in
		* /usr/include/machine/fpu.h under OSF/1.
		*/
		#define IEEE_TRAP_ENABLE_INV (1UL<<1) /* invalid op */
		#define IEEE_TRAP_ENABLE_DZE (1UL<<2) /* division by zero */
		#define IEEE_TRAP_ENABLE_OVF (1UL<<3) /* overflow */
		#define IEEE_TRAP_ENABLE_UNF (1UL<<4) /* underflow */
		#define IEEE_TRAP_ENABLE_INE (1UL<<5) /* inexact */
		#define IEEE_TRAP_ENABLE_DNO (1UL<<6) /* denorm */
		#define IEEE_TRAP_ENABLE_MASK (IEEE_TRAP_ENABLE_INV \| IEEE_TRAP_ENABLE_DZE \|\
		IEEE_TRAP_ENABLE_OVF \| IEEE_TRAP_ENABLE_UNF \|\
		IEEE_TRAP_ENABLE_INE \| IEEE_TRAP_ENABLE_DNO)

		/* Denorm and Underflow flushing */
		#define IEEE_MAP_DMZ (1UL<<12) /* Map denorm inputs to zero */
		#define IEEE_MAP_UMZ (1UL<<13) /* Map underflowed outputs to zero */

		#define IEEE_MAP_MASK (IEEE_MAP_DMZ \| IEEE_MAP_UMZ)

		/* status bits coming from fpcr: */
		#define IEEE_STATUS_INV (1UL<<17)
		#define IEEE_STATUS_DZE (1UL<<18)
		#define IEEE_STATUS_OVF (1UL<<19)
		#define IEEE_STATUS_UNF (1UL<<20)
		#define IEEE_STATUS_INE (1UL<<21)
		#define IEEE_STATUS_DNO (1UL<<22)

		#define IEEE_STATUS_MASK (IEEE_STATUS_INV \| IEEE_STATUS_DZE \| \
		IEEE_STATUS_OVF \| IEEE_STATUS_UNF \| \
		IEEE_STATUS_INE \| IEEE_STATUS_DNO)

		#define IEEE_SW_MASK (IEEE_TRAP_ENABLE_MASK \| \
		IEEE_STATUS_MASK \| IEEE_MAP_MASK)

		#define IEEE_CURRENT_RM_SHIFT 32
		#define IEEE_CURRENT_RM_MASK (3UL<<IEEE_CURRENT_RM_SHIFT)

		#define IEEE_STATUS_TO_EXCSUM_SHIFT 16

		#define IEEE_INHERIT (1UL<<63) /* inherit on thread create? */

		/*
		* Convert the software IEEE trap enable and status bits into the
		* hardware fpcr format.
		*
		* Digital Unix engineers receive my thanks for not defining the
		* software bits identical to the hardware bits. The chip designers
		* receive my thanks for making all the not-implemented fpcr bits
		* RAZ forcing us to use system calls to read/write this value.
		*/

		static inline unsigned long
		ieee_swcr_to_fpcr(unsigned long sw)
		{
		unsigned long fp;
		fp = (sw & IEEE_STATUS_MASK) << 35;
		fp \|= (sw & IEEE_MAP_DMZ) << 36;
		fp \|= (sw & IEEE_STATUS_MASK ? FPCR_SUM : 0);
		fp \|= (~sw & (IEEE_TRAP_ENABLE_INV
		\| IEEE_TRAP_ENABLE_DZE
		\| IEEE_TRAP_ENABLE_OVF)) << 48;
		fp \|= (~sw & (IEEE_TRAP_ENABLE_UNF \| IEEE_TRAP_ENABLE_INE)) << 57;
		fp \|= (sw & IEEE_MAP_UMZ ? FPCR_UNDZ \| FPCR_UNFD : 0);
		fp \|= (~sw & IEEE_TRAP_ENABLE_DNO) << 41;
		return fp;
		}

		static inline unsigned long
		ieee_fpcr_to_swcr(unsigned long fp)
		{
		unsigned long sw;
		sw = (fp >> 35) & IEEE_STATUS_MASK;
		sw \|= (fp >> 36) & IEEE_MAP_DMZ;
		sw \|= (~fp >> 48) & (IEEE_TRAP_ENABLE_INV
		\| IEEE_TRAP_ENABLE_DZE
		\| IEEE_TRAP_ENABLE_OVF);
		sw \|= (~fp >> 57) & (IEEE_TRAP_ENABLE_UNF \| IEEE_TRAP_ENABLE_INE);
		sw \|= (fp >> 47) & IEEE_MAP_UMZ;
		sw \|= (~fp >> 41) & IEEE_TRAP_ENABLE_DNO;
		return sw;
		}

		#ifdef __KERNEL__
		#include <uapi/asm/fpu.h>

		/* The following two functions don't need trapb/excb instructions
		around the mf_fpcr/mt_fpcr instructions because (a) the kernel
		@@ -192,6 +72,4 @@ extern void alpha_write_fp_reg (unsigned long reg, unsigned long val);
		extern unsigned long alpha_read_fp_reg_s (unsigned long reg);
		extern void alpha_write_fp_reg_s (unsigned long reg, unsigned long val);

		#endif /* __KERNEL__ */

		#endif /* __ASM_ALPHA_FPU_H */