Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 95a17a23 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 

* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6:
  drm/radeon: fix page flipping hangs on r300/r400
  drm/radeon: add pageflip hooks for fusion
parents 28db8376 c640e8ca

drivers/gpu/drm/radeon/r100.c

+0 −17
Original line number Diff line number Diff line
@@ -70,23 +70,6 @@ MODULE_FIRMWARE(FIRMWARE_R520); 


void r100_pre_page_flip(struct radeon_device *rdev, int crtc)

{

	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];

	u32 tmp;



	/* make sure flip is at vb rather than hb */

	tmp = RREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset);

	tmp &= ~RADEON_CRTC_OFFSET_FLIP_CNTL;

	/* make sure pending bit is asserted */

	tmp |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;

	WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, tmp);



	/* set pageflip to happen as late as possible in the vblank interval.

	 * same field for crtc1/2

	 */

	tmp = RREG32(RADEON_CRTC_GEN_CNTL);

	tmp &= ~RADEON_CRTC_VSTAT_MODE_MASK;

	WREG32(RADEON_CRTC_GEN_CNTL, tmp);



	/* enable the pflip int */

	radeon_irq_kms_pflip_irq_get(rdev, crtc);

}

drivers/gpu/drm/radeon/radeon_asic.c

+3 −0
Original line number Diff line number Diff line
@@ -834,6 +834,9 @@ static struct radeon_asic sumo_asic = { 
	.pm_finish = &evergreen_pm_finish,

	.pm_init_profile = &rs780_pm_init_profile,

	.pm_get_dynpm_state = &r600_pm_get_dynpm_state,

	.pre_page_flip = &evergreen_pre_page_flip,

	.page_flip = &evergreen_page_flip,

	.post_page_flip = &evergreen_post_page_flip,

};



static struct radeon_asic btc_asic = {

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

+2 −1
Original line number Diff line number Diff line
@@ -443,7 +443,7 @@ int radeon_crtc_do_set_base(struct drm_crtc *crtc, 
		       (target_fb->bits_per_pixel * 8));

	crtc_pitch |= crtc_pitch << 16;





	crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;

	if (tiling_flags & RADEON_TILING_MACRO) {

		if (ASIC_IS_R300(rdev))

			crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
@@ -502,6 +502,7 @@ int radeon_crtc_do_set_base(struct drm_crtc *crtc, 
	gen_cntl_val = RREG32(gen_cntl_reg);

	gen_cntl_val &= ~(0xf << 8);

	gen_cntl_val |= (format << 8);

	gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK;

	WREG32(gen_cntl_reg, gen_cntl_val);



	crtc_offset = (u32)base;