Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 954bce50 authored by Eric Anholt's avatar Eric Anholt
Browse files

agp/intel: Add a new Sandybridge HB/IG PCI ID combo. 



Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent 14bc490b

drivers/char/agp/intel-agp.c

+13 −4
Original line number Diff line number Diff line
@@ -66,6 +66,8 @@ 
#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG	    0x0046

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB  0x0100

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG  0x0102

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB  0x0104

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG  0x0106



/* cover 915 and 945 variants */

#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
@@ -101,7 +103,8 @@ 
		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB)

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)



extern int agp_memory_reserved;
@@ -317,7 +320,9 @@ static void intel_agp_insert_sg_entries(struct agp_memory *mem, 
	int i, j;

	u32 cache_bits = 0;



	if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB) {

	if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB ||

	    agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)

	{

		cache_bits = I830_PTE_SYSTEM_CACHED;

	}
@@ -732,8 +737,8 @@ static void intel_i830_init_gtt_entries(void) 
			gtt_entries = 0;

			break;

		}

	} else if (agp_bridge->dev->device ==

		   PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB) {

	} else if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB ||

		   agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB) {

		/*

		 * SandyBridge has new memory control reg at 0x50.w

		 */
@@ -1449,6 +1454,7 @@ static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) 
	case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB:

	case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB:

	case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB:

	case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB:

		*gtt_offset = *gtt_size = MB(2);

		break;

	default:
@@ -2456,6 +2462,8 @@ static const struct intel_driver_description { 
	    "HD Graphics", NULL, &intel_i965_driver },

	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG, 0,

	    "Sandybridge", NULL, &intel_i965_driver },

	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG, 0,

	    "Sandybridge", NULL, &intel_i965_driver },

	{ 0, 0, 0, NULL, NULL, NULL }

};
@@ -2663,6 +2671,7 @@ static struct pci_device_id agp_intel_pci_table[] = { 
	ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB),

	ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB),

	ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB),

	ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB),

	{ }

};