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Commit 925fe08b authored by Suravee Suthikulpanit's avatar Suravee Suthikulpanit Committed by Joerg Roedel
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iommu/amd: Re-enable IOMMU event log interrupt after handling. 



Current driver does not clear the IOMMU event log interrupt bit
in the IOMMU status register after processing an interrupt.
This causes the IOMMU hardware to generate event log interrupt only once.
This has been observed in both IOMMU v1 and V2 hardware.
This patch clears the bit by writing 1 to bit 1 of the IOMMU
status register (MMIO Offset 2020h)

Signed-off-by: default avatarSuravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: default avatarJoerg Roedel <joro@8bytes.org>
parent 07961ac7

drivers/iommu/amd_iommu.c

+3 −0
Original line number Original line Diff line number Diff line
@@ -703,6 +703,9 @@ static void iommu_poll_events(struct amd_iommu *iommu) 
	u32 head, tail;

	u32 head, tail;

	unsigned long flags;

	unsigned long flags;





	/* enable event interrupts again */

	writel(MMIO_STATUS_EVT_INT_MASK, iommu->mmio_base + MMIO_STATUS_OFFSET);



	spin_lock_irqsave(&iommu->lock, flags);

	spin_lock_irqsave(&iommu->lock, flags);





	head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);

	head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);

drivers/iommu/amd_iommu_types.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -99,6 +99,7 @@ 
#define PASID_MASK		0x000fffff

#define PASID_MASK		0x000fffff





/* MMIO status bits */

/* MMIO status bits */

#define MMIO_STATUS_EVT_INT_MASK	(1 << 1)

#define MMIO_STATUS_COM_WAIT_INT_MASK	(1 << 2)

#define MMIO_STATUS_COM_WAIT_INT_MASK	(1 << 2)

#define MMIO_STATUS_PPR_INT_MASK	(1 << 6)

#define MMIO_STATUS_PPR_INT_MASK	(1 << 6)