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Commit 9218e02b authored by Michael Buesch's avatar Michael Buesch Committed by John W. Linville
Browse files

[PATCH] bcm43xx: >1G and 64bit DMA support 



This is a rewrite of the bcm43xx DMA engine. It adds support
for >1G of memory (for chips that support the extension bits)
and 64-bit DMA (for chips that support it).

Signed-off-by: default avatarMichael Buesch <mb@bu3sch.de>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 3b4c7d64

drivers/net/wireless/bcm43xx/bcm43xx.h

+42 −16
Original line number Diff line number Diff line
@@ -33,14 +33,18 @@ 
#define BCM43xx_PCICFG_ICR		0x94



/* MMIO offsets */

#define BCM43xx_MMIO_DMA1_REASON	0x20

#define BCM43xx_MMIO_DMA1_IRQ_MASK	0x24

#define BCM43xx_MMIO_DMA2_REASON	0x28

#define BCM43xx_MMIO_DMA2_IRQ_MASK	0x2C

#define BCM43xx_MMIO_DMA3_REASON	0x30

#define BCM43xx_MMIO_DMA3_IRQ_MASK	0x34

#define BCM43xx_MMIO_DMA4_REASON	0x38

#define BCM43xx_MMIO_DMA4_IRQ_MASK	0x3C

#define BCM43xx_MMIO_DMA0_REASON	0x20

#define BCM43xx_MMIO_DMA0_IRQ_MASK	0x24

#define BCM43xx_MMIO_DMA1_REASON	0x28

#define BCM43xx_MMIO_DMA1_IRQ_MASK	0x2C

#define BCM43xx_MMIO_DMA2_REASON	0x30

#define BCM43xx_MMIO_DMA2_IRQ_MASK	0x34

#define BCM43xx_MMIO_DMA3_REASON	0x38

#define BCM43xx_MMIO_DMA3_IRQ_MASK	0x3C

#define BCM43xx_MMIO_DMA4_REASON	0x40

#define BCM43xx_MMIO_DMA4_IRQ_MASK	0x44

#define BCM43xx_MMIO_DMA5_REASON	0x48

#define BCM43xx_MMIO_DMA5_IRQ_MASK	0x4C

#define BCM43xx_MMIO_STATUS_BITFIELD	0x120

#define BCM43xx_MMIO_STATUS2_BITFIELD	0x124

#define BCM43xx_MMIO_GEN_IRQ_REASON	0x128
@@ -56,14 +60,27 @@ 
#define BCM43xx_MMIO_XMITSTAT_1		0x174

#define BCM43xx_MMIO_REV3PLUS_TSF_LOW	0x180 /* core rev >= 3 only */

#define BCM43xx_MMIO_REV3PLUS_TSF_HIGH	0x184 /* core rev >= 3 only */

#define BCM43xx_MMIO_DMA1_BASE		0x200

#define BCM43xx_MMIO_DMA2_BASE		0x220

#define BCM43xx_MMIO_DMA3_BASE		0x240

#define BCM43xx_MMIO_DMA4_BASE		0x260



/* 32-bit DMA */

#define BCM43xx_MMIO_DMA32_BASE0	0x200

#define BCM43xx_MMIO_DMA32_BASE1	0x220

#define BCM43xx_MMIO_DMA32_BASE2	0x240

#define BCM43xx_MMIO_DMA32_BASE3	0x260

#define BCM43xx_MMIO_DMA32_BASE4	0x280

#define BCM43xx_MMIO_DMA32_BASE5	0x2A0

/* 64-bit DMA */

#define BCM43xx_MMIO_DMA64_BASE0	0x200

#define BCM43xx_MMIO_DMA64_BASE1	0x240

#define BCM43xx_MMIO_DMA64_BASE2	0x280

#define BCM43xx_MMIO_DMA64_BASE3	0x2C0

#define BCM43xx_MMIO_DMA64_BASE4	0x300

#define BCM43xx_MMIO_DMA64_BASE5	0x340

/* PIO */

#define BCM43xx_MMIO_PIO1_BASE		0x300

#define BCM43xx_MMIO_PIO2_BASE		0x310

#define BCM43xx_MMIO_PIO3_BASE		0x320

#define BCM43xx_MMIO_PIO4_BASE		0x330



#define BCM43xx_MMIO_PHY_VER		0x3E0

#define BCM43xx_MMIO_PHY_RADIO		0x3E2

#define BCM43xx_MMIO_ANTENNA		0x3E8
@@ -233,8 +250,14 @@ 
#define BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK	0x20000



/* sbtmstatehigh state flags */

#define BCM43xx_SBTMSTATEHIGH_SERROR		0x1

#define BCM43xx_SBTMSTATEHIGH_BUSY		0x4

#define BCM43xx_SBTMSTATEHIGH_SERROR		0x00000001

#define BCM43xx_SBTMSTATEHIGH_BUSY		0x00000004

#define BCM43xx_SBTMSTATEHIGH_TIMEOUT		0x00000020

#define BCM43xx_SBTMSTATEHIGH_COREFLAGS		0x1FFF0000

#define BCM43xx_SBTMSTATEHIGH_DMA64BIT		0x10000000

#define BCM43xx_SBTMSTATEHIGH_GATEDCLK		0x20000000

#define BCM43xx_SBTMSTATEHIGH_BISTFAILED	0x40000000

#define BCM43xx_SBTMSTATEHIGH_BISTCOMPLETE	0x80000000



/* sbimstate flags */

#define BCM43xx_SBIMSTATE_IB_ERROR		0x20000
@@ -574,8 +597,11 @@ struct bcm43xx_dma { 
	struct bcm43xx_dmaring *tx_ring1;

	struct bcm43xx_dmaring *tx_ring2;

	struct bcm43xx_dmaring *tx_ring3;

	struct bcm43xx_dmaring *tx_ring4;

	struct bcm43xx_dmaring *tx_ring5;



	struct bcm43xx_dmaring *rx_ring0;

	struct bcm43xx_dmaring *rx_ring1; /* only available on core.rev < 5 */

	struct bcm43xx_dmaring *rx_ring3; /* only available on core.rev < 5 */

};



/* Data structures for PIO transmission, per 80211 core. */
@@ -739,7 +765,7 @@ struct bcm43xx_private { 


	/* Reason code of the last interrupt. */

	u32 irq_reason;

	u32 dma_reason[4];

	u32 dma_reason[6];

	/* saved irq enable/disable state bitfield. */

	u32 irq_savedstate;

	/* Link Quality calculation context. */

drivers/net/wireless/bcm43xx/bcm43xx_dma.c

+386 −197

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/wireless/bcm43xx/bcm43xx_dma.h

+214 −75
Original line number Diff line number Diff line
@@ -14,63 +14,179 @@ 
#define BCM43xx_DMAIRQ_NONFATALMASK	(1 << 13)

#define BCM43xx_DMAIRQ_RX_DONE		(1 << 16)



/* DMA controller register offsets. (relative to BCM43xx_DMA#_BASE) */

#define BCM43xx_DMA_TX_CONTROL		0x00

#define BCM43xx_DMA_TX_DESC_RING	0x04

#define BCM43xx_DMA_TX_DESC_INDEX	0x08

#define BCM43xx_DMA_TX_STATUS		0x0c

#define BCM43xx_DMA_RX_CONTROL		0x10

#define BCM43xx_DMA_RX_DESC_RING	0x14

#define BCM43xx_DMA_RX_DESC_INDEX	0x18

#define BCM43xx_DMA_RX_STATUS		0x1c



/* DMA controller channel control word values. */

#define BCM43xx_DMA_TXCTRL_ENABLE		(1 << 0)

#define BCM43xx_DMA_TXCTRL_SUSPEND		(1 << 1)

#define BCM43xx_DMA_TXCTRL_LOOPBACK		(1 << 2)

#define BCM43xx_DMA_TXCTRL_FLUSH		(1 << 4)

#define BCM43xx_DMA_RXCTRL_ENABLE		(1 << 0)

#define BCM43xx_DMA_RXCTRL_FRAMEOFF_MASK	0x000000fe

#define BCM43xx_DMA_RXCTRL_FRAMEOFF_SHIFT	1

#define BCM43xx_DMA_RXCTRL_PIO			(1 << 8)

/* DMA controller channel status word values. */

#define BCM43xx_DMA_TXSTAT_DPTR_MASK		0x00000fff

#define BCM43xx_DMA_TXSTAT_STAT_MASK		0x0000f000

#define BCM43xx_DMA_TXSTAT_STAT_DISABLED	0x00000000

#define BCM43xx_DMA_TXSTAT_STAT_ACTIVE		0x00001000

#define BCM43xx_DMA_TXSTAT_STAT_IDLEWAIT	0x00002000

#define BCM43xx_DMA_TXSTAT_STAT_STOPPED		0x00003000

#define BCM43xx_DMA_TXSTAT_STAT_SUSP		0x00004000

#define BCM43xx_DMA_TXSTAT_ERROR_MASK		0x000f0000

#define BCM43xx_DMA_TXSTAT_FLUSHED		(1 << 20)

#define BCM43xx_DMA_RXSTAT_DPTR_MASK		0x00000fff

#define BCM43xx_DMA_RXSTAT_STAT_MASK		0x0000f000

#define BCM43xx_DMA_RXSTAT_STAT_DISABLED	0x00000000

#define BCM43xx_DMA_RXSTAT_STAT_ACTIVE		0x00001000

#define BCM43xx_DMA_RXSTAT_STAT_IDLEWAIT	0x00002000

#define BCM43xx_DMA_RXSTAT_STAT_RESERVED	0x00003000

#define BCM43xx_DMA_RXSTAT_STAT_ERRORS		0x00004000

#define BCM43xx_DMA_RXSTAT_ERROR_MASK		0x000f0000



/* DMA descriptor control field values. */

#define BCM43xx_DMADTOR_BYTECNT_MASK		0x00001fff

#define BCM43xx_DMADTOR_DTABLEEND		(1 << 28) /* End of descriptor table */

#define BCM43xx_DMADTOR_COMPIRQ			(1 << 29) /* IRQ on completion request */

#define BCM43xx_DMADTOR_FRAMEEND		(1 << 30)

#define BCM43xx_DMADTOR_FRAMESTART		(1 << 31)



/*** 32-bit DMA Engine. ***/



/* 32-bit DMA controller registers. */

#define BCM43xx_DMA32_TXCTL				0x00

#define		BCM43xx_DMA32_TXENABLE			0x00000001

#define		BCM43xx_DMA32_TXSUSPEND			0x00000002

#define		BCM43xx_DMA32_TXLOOPBACK		0x00000004

#define		BCM43xx_DMA32_TXFLUSH			0x00000010

#define		BCM43xx_DMA32_TXADDREXT_MASK		0x00030000

#define		BCM43xx_DMA32_TXADDREXT_SHIFT		16

#define BCM43xx_DMA32_TXRING				0x04

#define BCM43xx_DMA32_TXINDEX				0x08

#define BCM43xx_DMA32_TXSTATUS				0x0C

#define		BCM43xx_DMA32_TXDPTR			0x00000FFF

#define		BCM43xx_DMA32_TXSTATE			0x0000F000

#define			BCM43xx_DMA32_TXSTAT_DISABLED	0x00000000

#define			BCM43xx_DMA32_TXSTAT_ACTIVE	0x00001000

#define			BCM43xx_DMA32_TXSTAT_IDLEWAIT	0x00002000

#define			BCM43xx_DMA32_TXSTAT_STOPPED	0x00003000

#define			BCM43xx_DMA32_TXSTAT_SUSP	0x00004000

#define		BCM43xx_DMA32_TXERROR			0x000F0000

#define			BCM43xx_DMA32_TXERR_NOERR	0x00000000

#define			BCM43xx_DMA32_TXERR_PROT	0x00010000

#define			BCM43xx_DMA32_TXERR_UNDERRUN	0x00020000

#define			BCM43xx_DMA32_TXERR_BUFREAD	0x00030000

#define			BCM43xx_DMA32_TXERR_DESCREAD	0x00040000

#define		BCM43xx_DMA32_TXACTIVE			0xFFF00000

#define BCM43xx_DMA32_RXCTL				0x10

#define		BCM43xx_DMA32_RXENABLE			0x00000001

#define		BCM43xx_DMA32_RXFROFF_MASK		0x000000FE

#define		BCM43xx_DMA32_RXFROFF_SHIFT		1

#define		BCM43xx_DMA32_RXDIRECTFIFO		0x00000100

#define		BCM43xx_DMA32_RXADDREXT_MASK		0x00030000

#define		BCM43xx_DMA32_RXADDREXT_SHIFT		16

#define BCM43xx_DMA32_RXRING				0x14

#define BCM43xx_DMA32_RXINDEX				0x18

#define BCM43xx_DMA32_RXSTATUS				0x1C

#define		BCM43xx_DMA32_RXDPTR			0x00000FFF

#define		BCM43xx_DMA32_RXSTATE			0x0000F000

#define			BCM43xx_DMA32_RXSTAT_DISABLED	0x00000000

#define			BCM43xx_DMA32_RXSTAT_ACTIVE	0x00001000

#define			BCM43xx_DMA32_RXSTAT_IDLEWAIT	0x00002000

#define			BCM43xx_DMA32_RXSTAT_STOPPED	0x00003000

#define		BCM43xx_DMA32_RXERROR			0x000F0000

#define			BCM43xx_DMA32_RXERR_NOERR	0x00000000

#define			BCM43xx_DMA32_RXERR_PROT	0x00010000

#define			BCM43xx_DMA32_RXERR_OVERFLOW	0x00020000

#define			BCM43xx_DMA32_RXERR_BUFWRITE	0x00030000

#define			BCM43xx_DMA32_RXERR_DESCREAD	0x00040000

#define		BCM43xx_DMA32_RXACTIVE			0xFFF00000



/* 32-bit DMA descriptor. */

struct bcm43xx_dmadesc32 {

	__le32 control;

	__le32 address;

} __attribute__((__packed__));

#define BCM43xx_DMA32_DCTL_BYTECNT		0x00001FFF

#define BCM43xx_DMA32_DCTL_ADDREXT_MASK		0x00030000

#define BCM43xx_DMA32_DCTL_ADDREXT_SHIFT	16

#define BCM43xx_DMA32_DCTL_DTABLEEND		0x10000000

#define BCM43xx_DMA32_DCTL_IRQ			0x20000000

#define BCM43xx_DMA32_DCTL_FRAMEEND		0x40000000

#define BCM43xx_DMA32_DCTL_FRAMESTART		0x80000000



/* Address field Routing value. */

#define BCM43xx_DMA32_ROUTING			0xC0000000

#define BCM43xx_DMA32_ROUTING_SHIFT		30

#define		BCM43xx_DMA32_NOTRANS		0x00000000

#define		BCM43xx_DMA32_CLIENTTRANS	0x40000000







/*** 64-bit DMA Engine. ***/



/* 64-bit DMA controller registers. */

#define BCM43xx_DMA64_TXCTL				0x00

#define		BCM43xx_DMA64_TXENABLE			0x00000001

#define		BCM43xx_DMA64_TXSUSPEND			0x00000002

#define		BCM43xx_DMA64_TXLOOPBACK		0x00000004

#define		BCM43xx_DMA64_TXFLUSH			0x00000010

#define		BCM43xx_DMA64_TXADDREXT_MASK		0x00030000

#define		BCM43xx_DMA64_TXADDREXT_SHIFT		16

#define BCM43xx_DMA64_TXINDEX				0x04

#define BCM43xx_DMA64_TXRINGLO				0x08

#define BCM43xx_DMA64_TXRINGHI				0x0C

#define BCM43xx_DMA64_TXSTATUS				0x10

#define		BCM43xx_DMA64_TXSTATDPTR		0x00001FFF

#define		BCM43xx_DMA64_TXSTAT			0xF0000000

#define			BCM43xx_DMA64_TXSTAT_DISABLED	0x00000000

#define			BCM43xx_DMA64_TXSTAT_ACTIVE	0x10000000

#define			BCM43xx_DMA64_TXSTAT_IDLEWAIT	0x20000000

#define			BCM43xx_DMA64_TXSTAT_STOPPED	0x30000000

#define			BCM43xx_DMA64_TXSTAT_SUSP	0x40000000

#define BCM43xx_DMA64_TXERROR				0x14

#define		BCM43xx_DMA64_TXERRDPTR			0x0001FFFF

#define		BCM43xx_DMA64_TXERR			0xF0000000

#define			BCM43xx_DMA64_TXERR_NOERR	0x00000000

#define			BCM43xx_DMA64_TXERR_PROT	0x10000000

#define			BCM43xx_DMA64_TXERR_UNDERRUN	0x20000000

#define			BCM43xx_DMA64_TXERR_TRANSFER	0x30000000

#define			BCM43xx_DMA64_TXERR_DESCREAD	0x40000000

#define			BCM43xx_DMA64_TXERR_CORE	0x50000000

#define BCM43xx_DMA64_RXCTL				0x20

#define		BCM43xx_DMA64_RXENABLE			0x00000001

#define		BCM43xx_DMA64_RXFROFF_MASK		0x000000FE

#define		BCM43xx_DMA64_RXFROFF_SHIFT		1

#define		BCM43xx_DMA64_RXDIRECTFIFO		0x00000100

#define		BCM43xx_DMA64_RXADDREXT_MASK		0x00030000

#define		BCM43xx_DMA64_RXADDREXT_SHIFT		16

#define BCM43xx_DMA64_RXINDEX				0x24

#define BCM43xx_DMA64_RXRINGLO				0x28

#define BCM43xx_DMA64_RXRINGHI				0x2C

#define BCM43xx_DMA64_RXSTATUS				0x30

#define		BCM43xx_DMA64_RXSTATDPTR		0x00001FFF

#define		BCM43xx_DMA64_RXSTAT			0xF0000000

#define			BCM43xx_DMA64_RXSTAT_DISABLED	0x00000000

#define			BCM43xx_DMA64_RXSTAT_ACTIVE	0x10000000

#define			BCM43xx_DMA64_RXSTAT_IDLEWAIT	0x20000000

#define			BCM43xx_DMA64_RXSTAT_STOPPED	0x30000000

#define			BCM43xx_DMA64_RXSTAT_SUSP	0x40000000

#define BCM43xx_DMA64_RXERROR				0x34

#define		BCM43xx_DMA64_RXERRDPTR			0x0001FFFF

#define		BCM43xx_DMA64_RXERR			0xF0000000

#define			BCM43xx_DMA64_RXERR_NOERR	0x00000000

#define			BCM43xx_DMA64_RXERR_PROT	0x10000000

#define			BCM43xx_DMA64_RXERR_UNDERRUN	0x20000000

#define			BCM43xx_DMA64_RXERR_TRANSFER	0x30000000

#define			BCM43xx_DMA64_RXERR_DESCREAD	0x40000000

#define			BCM43xx_DMA64_RXERR_CORE	0x50000000



/* 64-bit DMA descriptor. */

struct bcm43xx_dmadesc64 {

	__le32 control0;

	__le32 control1;

	__le32 address_low;

	__le32 address_high;

} __attribute__((__packed__));

#define BCM43xx_DMA64_DCTL0_DTABLEEND		0x10000000

#define BCM43xx_DMA64_DCTL0_IRQ			0x20000000

#define BCM43xx_DMA64_DCTL0_FRAMEEND		0x40000000

#define BCM43xx_DMA64_DCTL0_FRAMESTART		0x80000000

#define BCM43xx_DMA64_DCTL1_BYTECNT		0x00001FFF

#define BCM43xx_DMA64_DCTL1_ADDREXT_MASK	0x00030000

#define BCM43xx_DMA64_DCTL1_ADDREXT_SHIFT	16



/* Address field Routing value. */

#define BCM43xx_DMA64_ROUTING			0xC0000000

#define BCM43xx_DMA64_ROUTING_SHIFT		30

#define		BCM43xx_DMA64_NOTRANS		0x00000000

#define		BCM43xx_DMA64_CLIENTTRANS	0x80000000







struct bcm43xx_dmadesc_generic {

	union {

		struct bcm43xx_dmadesc32 dma32;

		struct bcm43xx_dmadesc64 dma64;

	} __attribute__((__packed__));

} __attribute__((__packed__));





/* Misc DMA constants */

#define BCM43xx_DMA_RINGMEMSIZE		PAGE_SIZE

#define BCM43xx_DMA_BUSADDRMAX		0x3FFFFFFF

#define BCM43xx_DMA_DMABUSADDROFFSET	(1 << 30)

#define BCM43xx_DMA1_RX_FRAMEOFFSET	30

#define BCM43xx_DMA4_RX_FRAMEOFFSET	0

#define BCM43xx_DMA0_RX_FRAMEOFFSET	30

#define BCM43xx_DMA3_RX_FRAMEOFFSET	0





/* DMA engine tuning knobs */

#define BCM43xx_TXRING_SLOTS		512

#define BCM43xx_RXRING_SLOTS		64

#define BCM43xx_DMA1_RXBUFFERSIZE	(2304 + 100)

#define BCM43xx_DMA4_RXBUFFERSIZE	16

#define BCM43xx_DMA0_RX_BUFFERSIZE	(2304 + 100)

#define BCM43xx_DMA3_RX_BUFFERSIZE	16

/* Suspend the tx queue, if less than this percent slots are free. */

#define BCM43xx_TXSUSPEND_PERCENT	20

/* Resume the tx queue, if more than this percent slots are free. */
@@ -86,17 +202,6 @@ struct bcm43xx_private; 
struct bcm43xx_xmitstatus;





struct bcm43xx_dmadesc {

	__le32 _control;

	__le32 _address;

} __attribute__((__packed__));



/* Macros to access the bcm43xx_dmadesc struct */

#define get_desc_ctl(desc)		le32_to_cpu((desc)->_control)

#define set_desc_ctl(desc, ctl)		do { (desc)->_control = cpu_to_le32(ctl); } while (0)

#define get_desc_addr(desc)		le32_to_cpu((desc)->_address)

#define set_desc_addr(desc, addr)	do { (desc)->_address = cpu_to_le32(addr); } while (0)



struct bcm43xx_dmadesc_meta {

	/* The kernel DMA-able buffer. */

	struct sk_buff *skb;
@@ -105,15 +210,14 @@ struct bcm43xx_dmadesc_meta { 
};



struct bcm43xx_dmaring {

	struct bcm43xx_private *bcm;

	/* Kernel virtual base address of the ring memory. */

	struct bcm43xx_dmadesc *vbase;

	/* DMA memory offset */

	dma_addr_t memoffset;

	/* (Unadjusted) DMA base bus-address of the ring memory. */

	dma_addr_t dmabase;

	void *descbase;

	/* Meta data about all descriptors. */

	struct bcm43xx_dmadesc_meta *meta;

	/* DMA Routing value. */

	u32 routing;

	/* (Unadjusted) DMA base bus-address of the ring memory. */

	dma_addr_t dmabase;

	/* Number of descriptor slots in the ring. */

	int nr_slots;

	/* Number of used descriptor slots. */
@@ -127,12 +231,14 @@ struct bcm43xx_dmaring { 
	u32 frameoffset;

	/* Descriptor buffer size. */

	u16 rx_buffersize;

	/* The MMIO base register of the DMA controller, this

	 * ring is posted to.

	 */

	/* The MMIO base register of the DMA controller. */

	u16 mmio_base;

	/* DMA controller index number (0-5). */

	int index;

	u8 tx:1,	/* TRUE, if this is a TX ring. */

	   dma64:1,	/* TRUE, if 64-bit DMA is enabled (FALSE if 32bit). */

	   suspended:1;	/* TRUE, if transfers are suspended on this ring. */

	struct bcm43xx_private *bcm;

#ifdef CONFIG_BCM43XX_DEBUG

	/* Maximum number of used slots. */

	int max_used_slots;
@@ -140,6 +246,34 @@ struct bcm43xx_dmaring { 
};





static inline

int bcm43xx_dma_desc2idx(struct bcm43xx_dmaring *ring,

			 struct bcm43xx_dmadesc_generic *desc)

{

	if (ring->dma64) {

		struct bcm43xx_dmadesc64 *dd64 = ring->descbase;

		return (int)(&(desc->dma64) - dd64);

	} else {

		struct bcm43xx_dmadesc32 *dd32 = ring->descbase;

		return (int)(&(desc->dma32) - dd32);

	}

}



static inline

struct bcm43xx_dmadesc_generic * bcm43xx_dma_idx2desc(struct bcm43xx_dmaring *ring,

						      int slot,

						      struct bcm43xx_dmadesc_meta **meta)

{

	*meta = &(ring->meta[slot]);

	if (ring->dma64) {

		struct bcm43xx_dmadesc64 *dd64 = ring->descbase;

		return (struct bcm43xx_dmadesc_generic *)(&(dd64[slot]));

	} else {

		struct bcm43xx_dmadesc32 *dd32 = ring->descbase;

		return (struct bcm43xx_dmadesc_generic *)(&(dd32[slot]));

	}

}



static inline

u32 bcm43xx_dma_read(struct bcm43xx_dmaring *ring,

		     u16 offset)
@@ -159,9 +293,13 @@ int bcm43xx_dma_init(struct bcm43xx_private *bcm); 
void bcm43xx_dma_free(struct bcm43xx_private *bcm);



int bcm43xx_dmacontroller_rx_reset(struct bcm43xx_private *bcm,

				   u16 dmacontroller_mmio_base);

				   u16 dmacontroller_mmio_base,

				   int dma64);

int bcm43xx_dmacontroller_tx_reset(struct bcm43xx_private *bcm,

				   u16 dmacontroller_mmio_base);

				   u16 dmacontroller_mmio_base,

				   int dma64);



u16 bcm43xx_dmacontroller_base(int dma64bit, int dmacontroller_idx);



void bcm43xx_dma_tx_suspend(struct bcm43xx_dmaring *ring);

void bcm43xx_dma_tx_resume(struct bcm43xx_dmaring *ring);
@@ -173,7 +311,6 @@ int bcm43xx_dma_tx(struct bcm43xx_private *bcm, 
		   struct ieee80211_txb *txb);

void bcm43xx_dma_rx(struct bcm43xx_dmaring *ring);





#else /* CONFIG_BCM43XX_DMA */
@@ -188,13 +325,15 @@ void bcm43xx_dma_free(struct bcm43xx_private *bcm) 
}

static inline

int bcm43xx_dmacontroller_rx_reset(struct bcm43xx_private *bcm,

				   u16 dmacontroller_mmio_base)

				   u16 dmacontroller_mmio_base,

				   int dma64)

{

	return 0;

}

static inline

int bcm43xx_dmacontroller_tx_reset(struct bcm43xx_private *bcm,

				   u16 dmacontroller_mmio_base)

				   u16 dmacontroller_mmio_base,

				   int dma64)

{

	return 0;

}

drivers/net/wireless/bcm43xx/bcm43xx_main.c

+49 −36
Original line number Diff line number Diff line
@@ -1371,6 +1371,7 @@ void bcm43xx_wireless_core_reset(struct bcm43xx_private *bcm, int connect_phy) 
	if ((bcm43xx_core_enabled(bcm)) &&

	    !bcm43xx_using_pio(bcm)) {

//FIXME: Do we _really_ want #ifndef CONFIG_BCM947XX here?

#if 0

#ifndef CONFIG_BCM947XX

		/* reset all used DMA controllers. */

		bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
@@ -1380,6 +1381,7 @@ void bcm43xx_wireless_core_reset(struct bcm43xx_private *bcm, int connect_phy) 
		bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);

		if (bcm->current_core->rev < 5)

			bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);

#endif

#endif

	}

	if (bcm43xx_status(bcm) == BCM43xx_STAT_SHUTTINGDOWN) {
@@ -1671,8 +1673,9 @@ static void handle_irq_beacon(struct bcm43xx_private *bcm) 
static void bcm43xx_interrupt_tasklet(struct bcm43xx_private *bcm)

{

	u32 reason;

	u32 dma_reason[4];

	int activity = 0;

	u32 dma_reason[6];

	u32 merged_dma_reason = 0;

	int i, activity = 0;

	unsigned long flags;



#ifdef CONFIG_BCM43XX_DEBUG
@@ -1684,10 +1687,10 @@ static void bcm43xx_interrupt_tasklet(struct bcm43xx_private *bcm) 


	spin_lock_irqsave(&bcm->irq_lock, flags);

	reason = bcm->irq_reason;

	dma_reason[0] = bcm->dma_reason[0];

	dma_reason[1] = bcm->dma_reason[1];

	dma_reason[2] = bcm->dma_reason[2];

	dma_reason[3] = bcm->dma_reason[3];

	for (i = 5; i >= 0; i--) {

		dma_reason[i] = bcm->dma_reason[i];

		merged_dma_reason |= dma_reason[i];

	}



	if (unlikely(reason & BCM43xx_IRQ_XMIT_ERROR)) {

		/* TX error. We get this when Template Ram is written in wrong endianess
@@ -1698,27 +1701,25 @@ static void bcm43xx_interrupt_tasklet(struct bcm43xx_private *bcm) 
		printkl(KERN_ERR PFX "FATAL ERROR: BCM43xx_IRQ_XMIT_ERROR\n");

		bcmirq_handled(BCM43xx_IRQ_XMIT_ERROR);

	}

	if (unlikely((dma_reason[0] & BCM43xx_DMAIRQ_FATALMASK) |

		     (dma_reason[1] & BCM43xx_DMAIRQ_FATALMASK) |

		     (dma_reason[2] & BCM43xx_DMAIRQ_FATALMASK) |

		     (dma_reason[3] & BCM43xx_DMAIRQ_FATALMASK))) {

	if (unlikely(merged_dma_reason & BCM43xx_DMAIRQ_FATALMASK)) {

		printkl(KERN_ERR PFX "FATAL ERROR: Fatal DMA error: "

				     "0x%08X, 0x%08X, 0x%08X, 0x%08X\n",

				     "0x%08X, 0x%08X, 0x%08X, "

				     "0x%08X, 0x%08X, 0x%08X\n",

		        dma_reason[0], dma_reason[1],

			dma_reason[2], dma_reason[3]);

			dma_reason[2], dma_reason[3],

			dma_reason[4], dma_reason[5]);

		bcm43xx_controller_restart(bcm, "DMA error");

		mmiowb();

		spin_unlock_irqrestore(&bcm->irq_lock, flags);

		return;

	}

	if (unlikely((dma_reason[0] & BCM43xx_DMAIRQ_NONFATALMASK) |

		     (dma_reason[1] & BCM43xx_DMAIRQ_NONFATALMASK) |

		     (dma_reason[2] & BCM43xx_DMAIRQ_NONFATALMASK) |

		     (dma_reason[3] & BCM43xx_DMAIRQ_NONFATALMASK))) {

	if (unlikely(merged_dma_reason & BCM43xx_DMAIRQ_NONFATALMASK)) {

		printkl(KERN_ERR PFX "DMA error: "

				     "0x%08X, 0x%08X, 0x%08X, 0x%08X\n",

				     "0x%08X, 0x%08X, 0x%08X, "

				     "0x%08X, 0x%08X, 0x%08X\n",

		        dma_reason[0], dma_reason[1],

			dma_reason[2], dma_reason[3]);

			dma_reason[2], dma_reason[3],

			dma_reason[4], dma_reason[5]);

	}



	if (reason & BCM43xx_IRQ_PS) {
@@ -1753,8 +1754,6 @@ static void bcm43xx_interrupt_tasklet(struct bcm43xx_private *bcm) 
	}



	/* Check the DMA reason registers for received data. */

	assert(!(dma_reason[1] & BCM43xx_DMAIRQ_RX_DONE));

	assert(!(dma_reason[2] & BCM43xx_DMAIRQ_RX_DONE));

	if (dma_reason[0] & BCM43xx_DMAIRQ_RX_DONE) {

		if (bcm43xx_using_pio(bcm))

			bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue0);
@@ -1762,13 +1761,17 @@ static void bcm43xx_interrupt_tasklet(struct bcm43xx_private *bcm) 
			bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring0);

		/* We intentionally don't set "activity" to 1, here. */

	}

	assert(!(dma_reason[1] & BCM43xx_DMAIRQ_RX_DONE));

	assert(!(dma_reason[2] & BCM43xx_DMAIRQ_RX_DONE));

	if (dma_reason[3] & BCM43xx_DMAIRQ_RX_DONE) {

		if (bcm43xx_using_pio(bcm))

			bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue3);

		else

			bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring1);

			bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring3);

		activity = 1;

	}

	assert(!(dma_reason[4] & BCM43xx_DMAIRQ_RX_DONE));

	assert(!(dma_reason[5] & BCM43xx_DMAIRQ_RX_DONE));

	bcmirq_handled(BCM43xx_IRQ_RX);



	if (reason & BCM43xx_IRQ_XMIT_STATUS) {
@@ -1825,14 +1828,18 @@ static void bcm43xx_interrupt_ack(struct bcm43xx_private *bcm, u32 reason) 


	bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, reason);



	bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_REASON,

	bcm43xx_write32(bcm, BCM43xx_MMIO_DMA0_REASON,

			bcm->dma_reason[0]);

	bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_REASON,

	bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_REASON,

			bcm->dma_reason[1]);

	bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_REASON,

	bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_REASON,

			bcm->dma_reason[2]);

	bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_REASON,

	bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_REASON,

			bcm->dma_reason[3]);

	bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_REASON,

			bcm->dma_reason[4]);

	bcm43xx_write32(bcm, BCM43xx_MMIO_DMA5_REASON,

			bcm->dma_reason[5]);

}



/* Interrupt handler top-half */
@@ -1860,14 +1867,18 @@ static irqreturn_t bcm43xx_interrupt_handler(int irq, void *dev_id, struct pt_re 
	if (!reason)

		goto out;



	bcm->dma_reason[0] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA1_REASON)

			     & 0x0001dc00;

	bcm->dma_reason[1] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA2_REASON)

			     & 0x0000dc00;

	bcm->dma_reason[2] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA3_REASON)

			     & 0x0000dc00;

	bcm->dma_reason[3] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA4_REASON)

			     & 0x0001dc00;

	bcm->dma_reason[0] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA0_REASON)

			     & 0x0001DC00;

	bcm->dma_reason[1] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA1_REASON)

			     & 0x0000DC00;

	bcm->dma_reason[2] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA2_REASON)

			     & 0x0000DC00;

	bcm->dma_reason[3] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA3_REASON)

			     & 0x0001DC00;

	bcm->dma_reason[4] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA4_REASON)

			     & 0x0000DC00;

	bcm->dma_reason[5] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA5_REASON)

			     & 0x0000DC00;



	bcm43xx_interrupt_ack(bcm, reason);
@@ -2448,10 +2459,12 @@ static int bcm43xx_chip_init(struct bcm43xx_private *bcm) 
		bcm43xx_write32(bcm, 0x018C, 0x02000000);

	}

	bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0x00004000);

	bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_IRQ_MASK, 0x0001DC00);

	bcm43xx_write32(bcm, BCM43xx_MMIO_DMA0_IRQ_MASK, 0x0001DC00);

	bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_IRQ_MASK, 0x0000DC00);

	bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_IRQ_MASK, 0x0000DC00);

	bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_IRQ_MASK, 0x0000DC00);

	bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_IRQ_MASK, 0x0001DC00);

	bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_IRQ_MASK, 0x0001DC00);

	bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_IRQ_MASK, 0x0000DC00);

	bcm43xx_write32(bcm, BCM43xx_MMIO_DMA5_IRQ_MASK, 0x0000DC00);



	value32 = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);

	value32 |= 0x00100000;