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Commit 91f1b705 authored by Andi Kleen's avatar Andi Kleen Committed by Ingo Molnar
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perf/x86/intel: Add Broadwell core support 



Add Broadwell support for Broadwell to perf.

The basic support is very similar to Haswell. We use the new cache
event list added for Haswell earlier. The only differences
are a few bits related to remote nodes. To avoid an extra,
mostly identical, table these are patched up in the initialization code.

The constraint list has one new event that needs to be handled over Haswell.

Includes code and testing from Kan Liang.

Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1424225886-18652-2-git-send-email-andi@firstfloor.org


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 0f1b5ca2

arch/x86/kernel/cpu/perf_event_intel.c

+47 −0
Original line number Diff line number Diff line
@@ -220,6 +220,15 @@ static struct event_constraint intel_hsw_event_constraints[] = { 
	EVENT_CONSTRAINT_END

};



struct event_constraint intel_bdw_event_constraints[] = {

	FIXED_EVENT_CONSTRAINT(0x00c0, 0),	/* INST_RETIRED.ANY */

	FIXED_EVENT_CONSTRAINT(0x003c, 1),	/* CPU_CLK_UNHALTED.CORE */

	FIXED_EVENT_CONSTRAINT(0x0300, 2),	/* CPU_CLK_UNHALTED.REF */

	INTEL_UEVENT_CONSTRAINT(0x148, 0x4),	/* L1D_PEND_MISS.PENDING */

	INTEL_EVENT_CONSTRAINT(0xa3, 0x4),	/* CYCLE_ACTIVITY.* */

	EVENT_CONSTRAINT_END

};



static u64 intel_pmu_event_map(int hw_event)

{

	return intel_perfmon_event_map[hw_event];
@@ -453,6 +462,12 @@ static __initconst const u64 snb_hw_cache_event_ids 
					 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)

#define HSW_LLC_ACCESS			HSW_ANY_RESPONSE



#define BDW_L3_MISS_LOCAL		BIT(26)

#define BDW_L3_MISS			(BDW_L3_MISS_LOCAL| \

					 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \

					 HSW_L3_MISS_REMOTE_HOP2P)





static __initconst const u64 hsw_hw_cache_event_ids

				[PERF_COUNT_HW_CACHE_MAX]

				[PERF_COUNT_HW_CACHE_OP_MAX]
@@ -2730,6 +2745,38 @@ __init int intel_pmu_init(void) 
		pr_cont("Haswell events, ");

		break;



	case 61: /* 14nm Broadwell Core-M */

	case 86: /* 14nm Broadwell Xeon D */

		x86_pmu.late_ack = true;

		memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));

		memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));



		/* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */

		hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |

									 BDW_L3_MISS|HSW_SNOOP_DRAM;

		hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|

									  HSW_SNOOP_DRAM;

		hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|

									     BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;

		hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|

									      BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;



		intel_pmu_lbr_init_snb();



		x86_pmu.event_constraints = intel_bdw_event_constraints;

		x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;

		x86_pmu.extra_regs = intel_snbep_extra_regs;

		x86_pmu.pebs_aliases = intel_pebs_aliases_snb;

		/* all extra regs are per-cpu when HT is on */

		x86_pmu.er_flags |= ERF_HAS_RSP_1;

		x86_pmu.er_flags |= ERF_NO_HT_SHARING;



		x86_pmu.hw_config = hsw_hw_config;

		x86_pmu.get_event_constraints = hsw_get_event_constraints;

		x86_pmu.cpu_events = hsw_events_attrs;

		pr_cont("Broadwell events, ");

		break;



	default:

		switch (x86_pmu.version) {

		case 1: